From 456a925c6177d65ed63d6518cd7fdad3e6502ae6 Mon Sep 17 00:00:00 2001
From: Bill Wendling <isanbard@gmail.com>
Date: Thu, 4 Aug 2011 00:32:58 +0000
Subject: [PATCH] Only access both operands of an INSERT_SUBVECTOR if it is an
 INSERT_SUBVECTOR. Fixes PR10527.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136853 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelLowering.cpp | 19 ++++++++++---------
 test/CodeGen/X86/crash.ll          | 23 +++++++++++++++++++++++
 2 files changed, 33 insertions(+), 9 deletions(-)

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 56971520321..92451e5198d 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -12298,16 +12298,17 @@ static bool CanFoldXORWithAllOnes(const SDNode *N) {
 
   // Sometimes the operand may come from a insert_subvector building a 256-bit
   // allones vector
-  SDValue V1 = N->getOperand(0);
-  SDValue V2 = N->getOperand(1);
-
   if (VT.getSizeInBits() == 256 &&
-      N->getOpcode() == ISD::INSERT_SUBVECTOR &&
-      V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
-      V1.getOperand(0).getOpcode() == ISD::UNDEF &&
-      ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
-      ISD::isBuildVectorAllOnes(V2.getNode()))
-    return true;
+      N->getOpcode() == ISD::INSERT_SUBVECTOR) {
+    SDValue V1 = N->getOperand(0);
+    SDValue V2 = N->getOperand(1);
+
+    if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
+        V1.getOperand(0).getOpcode() == ISD::UNDEF &&
+        ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
+        ISD::isBuildVectorAllOnes(V2.getNode()))
+      return true;
+  }
 
   return false;
 }
diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll
index db1e99967c9..6f4bf6d31fa 100644
--- a/test/CodeGen/X86/crash.ll
+++ b/test/CodeGen/X86/crash.ll
@@ -341,3 +341,26 @@ CF77:
     br label %CF77
 }
 
+; PR10527
+define void @pr10527() nounwind uwtable {
+entry:
+  br label %"4"
+
+"3":
+  %0 = load <2 x i32>* null, align 8
+  %1 = xor <2 x i32> zeroinitializer, %0
+  %2 = and <2 x i32> %1, %6
+  %3 = or <2 x i32> undef, %2
+  %4 = and <2 x i32> %3, undef
+  store <2 x i32> %4, <2 x i32>* undef
+  %5 = load <2 x i32>* undef, align 1
+  br label %"4"
+
+"4":
+  %6 = phi <2 x i32> [ %5, %"3" ], [ zeroinitializer, %entry ]
+  %7 = icmp ult i32 undef, undef
+  br i1 %7, label %"3", label %"5"
+
+"5":
+  ret void
+}