mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
[PowerPC] Add assembler support for mcrfs and friends
Fill out our support for the floating-point status and control register instructions (mcrfs and friends). As it turns out, these are necessary for compiling src/test/harness_fp.h in TBB for PowerPC. Thanks to Raf Schietekat for reporting the issue! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226070 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
ef7d38d35a
commit
4572a0a0a2
@ -7718,7 +7718,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
|
||||
|
||||
// Restore FPSCR value.
|
||||
BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
|
||||
BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
|
||||
} else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
|
||||
MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
|
||||
MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
|
||||
|
@ -945,6 +945,25 @@ class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
||||
let Inst{31} = 0;
|
||||
}
|
||||
|
||||
class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
||||
InstrItinClass itin>
|
||||
: I<opcode, OOL, IOL, asmstr, itin> {
|
||||
bits<3> BF;
|
||||
bit W;
|
||||
bits<4> U;
|
||||
|
||||
bit RC = 0;
|
||||
|
||||
let Inst{6-8} = BF;
|
||||
let Inst{9-10} = 0;
|
||||
let Inst{11-14} = 0;
|
||||
let Inst{15} = W;
|
||||
let Inst{16-19} = U;
|
||||
let Inst{20} = 0;
|
||||
let Inst{21-30} = xo;
|
||||
let Inst{31} = RC;
|
||||
}
|
||||
|
||||
class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
|
||||
bits<6> opcode2, bits<2> xo2,
|
||||
dag OOL, dag IOL, string asmstr,
|
||||
@ -1081,6 +1100,25 @@ class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
||||
let Inst{31} = RC;
|
||||
}
|
||||
|
||||
class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
||||
InstrItinClass itin, list<dag>pattern>
|
||||
: I<opcode, OOL, IOL, asmstr, itin> {
|
||||
bit L;
|
||||
bits<8> FLM;
|
||||
bit W;
|
||||
bits<5> FRB;
|
||||
|
||||
bit RC = 0; // set by isDOT
|
||||
let Pattern = pattern;
|
||||
|
||||
let Inst{6} = L;
|
||||
let Inst{7-14} = FLM;
|
||||
let Inst{15} = W;
|
||||
let Inst{16-20} = FRB;
|
||||
let Inst{21-30} = xo;
|
||||
let Inst{31} = RC;
|
||||
}
|
||||
|
||||
// 1.7.10 XS-Form - SRADI.
|
||||
class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
|
||||
InstrItinClass itin, list<dag> pattern>
|
||||
|
@ -2193,15 +2193,20 @@ let Uses = [RM], Defs = [RM] in {
|
||||
def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
|
||||
"mtfsb1 $FM", IIC_IntMTFSB0, []>,
|
||||
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
||||
def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
|
||||
"mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
|
||||
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
||||
let isCodeGenOnly = 1 in
|
||||
def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
|
||||
"mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
|
||||
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
||||
}
|
||||
let Uses = [RM] in {
|
||||
def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
|
||||
"mffs $rT", IIC_IntMFFS,
|
||||
[(set f64:$rT, (PPCmffs))]>,
|
||||
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
||||
|
||||
let Defs = [CR1] in
|
||||
def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
|
||||
"mffs. $rT", IIC_IntMFFS, []>, isDOT;
|
||||
}
|
||||
|
||||
|
||||
@ -3187,6 +3192,28 @@ def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
|
||||
def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
|
||||
"mtmsrd $RS, $L", IIC_SprMTMSRD>;
|
||||
|
||||
def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
|
||||
"mcrfs $BF, $BFA", IIC_BrMCR>;
|
||||
|
||||
def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
|
||||
"mtfsfi $BF, $U, $W", IIC_IntMFFS>;
|
||||
|
||||
def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
|
||||
"mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
|
||||
|
||||
def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
|
||||
def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
|
||||
|
||||
def MTFSF : XFLForm_1<63, 711, (outs),
|
||||
(ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
|
||||
"mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
|
||||
def MTFSFo : XFLForm_1<63, 711, (outs),
|
||||
(ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
|
||||
"mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
|
||||
|
||||
def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
|
||||
def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
|
||||
|
||||
def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
|
||||
"slbie $RB", IIC_SprSLBIE, []>;
|
||||
|
||||
|
@ -321,6 +321,24 @@
|
||||
# CHECK: mffs 2
|
||||
0xfc 0x40 0x04 0x8e
|
||||
|
||||
# CHECK: mffs. 7
|
||||
0xfc 0xe0 0x04 0x8f
|
||||
|
||||
# CHECK: mcrfs 4, 5
|
||||
0xfe 0x14 0x00 0x80
|
||||
|
||||
# CHECK: mtfsfi 5, 2, 1
|
||||
0xfe 0x81 0x21 0x0c
|
||||
|
||||
# CHECK: mtfsfi. 5, 2, 1
|
||||
0xfe 0x81 0x21 0x0d
|
||||
|
||||
# CHECK: mtfsf 127, 8, 1, 1
|
||||
0xfe 0xff 0x45 0x8e
|
||||
|
||||
# CHECK: mtfsf. 125, 8, 1, 1
|
||||
0xfe 0xfb 0x45 0x8f
|
||||
|
||||
# CHECK: mtfsb0 31
|
||||
0xff 0xe0 0x00 0x8c
|
||||
|
||||
|
@ -359,15 +359,36 @@
|
||||
# CHECK-BE: mffs 2 # encoding: [0xfc,0x40,0x04,0x8e]
|
||||
# CHECK-LE: mffs 2 # encoding: [0x8e,0x04,0x40,0xfc]
|
||||
mffs 2
|
||||
# FIXME: mffs. 2
|
||||
|
||||
# FIXME: mcrfs 2, 3
|
||||
|
||||
# FIXME: mtfsfi 2, 3, 1
|
||||
# FIXME: mtfsfi. 2, 3, 1
|
||||
# FIXME: mtfsf 2, 3, 1, 1
|
||||
# FIXME: mtfsf. 2, 3, 1, 1
|
||||
|
||||
# CHECK-BE: mffs. 7 # encoding: [0xfc,0xe0,0x04,0x8f]
|
||||
# CHECK-LE: mffs. 7 # encoding: [0x8f,0x04,0xe0,0xfc]
|
||||
mffs. 7
|
||||
# CHECK-BE: mcrfs 4, 5 # encoding: [0xfe,0x14,0x00,0x80]
|
||||
# CHECK-LE: mcrfs 4, 5 # encoding: [0x80,0x00,0x14,0xfe]
|
||||
mcrfs 4, 5
|
||||
# CHECK-BE: mtfsfi 5, 2, 1 # encoding: [0xfe,0x81,0x21,0x0c]
|
||||
# CHECK-LE: mtfsfi 5, 2, 1 # encoding: [0x0c,0x21,0x81,0xfe]
|
||||
mtfsfi 5, 2, 1
|
||||
# CHECK-BE: mtfsfi. 5, 2, 1 # encoding: [0xfe,0x81,0x21,0x0d]
|
||||
# CHECK-LE: mtfsfi. 5, 2, 1 # encoding: [0x0d,0x21,0x81,0xfe]
|
||||
mtfsfi. 5, 2, 1
|
||||
# CHECK-BE: mtfsfi 6, 2, 0 # encoding: [0xff,0x00,0x21,0x0c]
|
||||
# CHECK-LE: mtfsfi 6, 2, 0 # encoding: [0x0c,0x21,0x00,0xff]
|
||||
mtfsfi 6, 2
|
||||
# CHECK-BE: mtfsfi. 6, 2, 0 # encoding: [0xff,0x00,0x21,0x0d]
|
||||
# CHECK-LE: mtfsfi. 6, 2, 0 # encoding: [0x0d,0x21,0x00,0xff]
|
||||
mtfsfi. 6, 2
|
||||
# CHECK-BE: mtfsf 127, 8, 1, 1 # encoding: [0xfe,0xff,0x45,0x8e]
|
||||
# CHECK-LE: mtfsf 127, 8, 1, 1 # encoding: [0x8e,0x45,0xff,0xfe]
|
||||
mtfsf 127, 8, 1, 1
|
||||
# CHECK-BE: mtfsf. 125, 8, 1, 1 # encoding: [0xfe,0xfb,0x45,0x8f]
|
||||
# CHECK-LE: mtfsf. 125, 8, 1, 1 # encoding: [0x8f,0x45,0xfb,0xfe]
|
||||
mtfsf. 125, 8, 1, 1
|
||||
# CHECK-BE: mtfsf 127, 6, 0, 0 # encoding: [0xfc,0xfe,0x35,0x8e]
|
||||
# CHECK-LE: mtfsf 127, 6, 0, 0 # encoding: [0x8e,0x35,0xfe,0xfc]
|
||||
mtfsf 127, 6
|
||||
# CHECK-BE: mtfsf. 125, 6, 0, 0 # encoding: [0xfc,0xfa,0x35,0x8f]
|
||||
# CHECK-LE: mtfsf. 125, 6, 0, 0 # encoding: [0x8f,0x35,0xfa,0xfc]
|
||||
mtfsf. 125, 6
|
||||
# CHECK-BE: mtfsb0 31 # encoding: [0xff,0xe0,0x00,0x8c]
|
||||
# CHECK-LE: mtfsb0 31 # encoding: [0x8c,0x00,0xe0,0xff]
|
||||
mtfsb0 31
|
||||
|
Loading…
Reference in New Issue
Block a user