6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-26 23:55:02 +00:00
Code Issues Projects Releases Wiki Activity

[PowerPC] Add some special @got@tprel fixup cases

Browse Source 
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.

However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.

The same applies for the @got@dtprel variants.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand 2013-07-05 13:49:46 +00:00
parent 47734db936
commit 457571ed69
2 changed files with 40 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
View File

@ -228,9 +228,29 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
case MCSymbolRefExpr::VK_PPC_GOT_TLSLD_HA:
Type = ELF::R_PPC64_GOT_TLSLD16_HA;
break;
case MCSymbolRefExpr::VK_PPC_GOT_TPREL:
/* We don't have R_PPC64_GOT_TPREL16, but since GOT offsets
are always 4-aligned, we can use R_PPC64_GOT_TPREL16_DS. */
Type = ELF::R_PPC64_GOT_TPREL16_DS;
break;
case MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO:
/* We don't have R_PPC64_GOT_TPREL16_LO, but since GOT offsets
are always 4-aligned, we can use R_PPC64_GOT_TPREL16_LO_DS. */
Type = ELF::R_PPC64_GOT_TPREL16_LO_DS;
break;
case MCSymbolRefExpr::VK_PPC_GOT_TPREL_HI:
Type = ELF::R_PPC64_GOT_TPREL16_HI;
break;
case MCSymbolRefExpr::VK_PPC_GOT_DTPREL:
/* We don't have R_PPC64_GOT_DTPREL16, but since GOT offsets
are always 4-aligned, we can use R_PPC64_GOT_DTPREL16_DS. */
Type = ELF::R_PPC64_GOT_DTPREL16_DS;
break;
case MCSymbolRefExpr::VK_PPC_GOT_DTPREL_LO:
/* We don't have R_PPC64_GOT_DTPREL16_LO, but since GOT offsets
are always 4-aligned, we can use R_PPC64_GOT_DTPREL16_LO_DS. */
Type = ELF::R_PPC64_GOT_DTPREL16_LO_DS;
break;
case MCSymbolRefExpr::VK_PPC_GOT_TPREL_HA:
Type = ELF::R_PPC64_GOT_TPREL16_HA;
break;

20
test/MC/PowerPC/ppc64-fixups.s
View File

@ -318,6 +318,16 @@ base:
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HI target 0x0
addis 3, 2, target@got@tprel@h
# CHECK: addis 3, 2, target@got@tprel@l # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
addis 3, 2, target@got@tprel@l
# CHECK: addis 3, 2, target@got@tprel # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0
addis 3, 2, target@got@tprel
# CHECK: ld 1, target@got@tprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0
@ -338,6 +348,16 @@ base:
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HI target 0x0
addis 3, 2, target@got@dtprel@h
# CHECK: addis 3, 2, target@got@dtprel@l # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel@l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0
addis 3, 2, target@got@dtprel@l
# CHECK: addis 3, 2, target@got@dtprel # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0
addis 3, 2, target@got@dtprel
# CHECK: ld 1, target@got@dtprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0