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Split the file MipsAsmBackend.cpp in Split the file MipsAsmBackend.cpp and Split the file MipsAsmBackend.h.
Differential Revision: http://llvm-reviews.chandlerc.com/D3134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204921 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -1,4 +1,4 @@
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//===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===//
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//===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -7,12 +7,13 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
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// This file implements the MipsAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "MipsFixupKinds.h"
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#include "MCTargetDesc/MipsFixupKinds.h"
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#include "MCTargetDesc/MipsAsmBackend.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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@ -106,208 +107,162 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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return Value;
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}
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namespace {
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class MipsAsmBackend : public MCAsmBackend {
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Triple::OSType OSType;
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bool IsLittle; // Big or little endian
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bool Is64Bit; // 32 or 64 bit words
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MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const {
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return createMipsELFObjectWriter(OS,
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MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
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}
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public:
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MipsAsmBackend(const Target &T, Triple::OSType _OSType,
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bool _isLittle, bool _is64Bit)
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:MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
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/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
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/// data fragment, at the offset specified by the fixup and following the
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/// fixup kind as appropriate.
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void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value) const {
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MCFixupKind Kind = Fixup.getKind();
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Value = adjustFixupValue(Fixup, Value);
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createMipsELFObjectWriter(OS,
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MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
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if (!Value)
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return; // Doesn't change encoding.
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// Where do we start in the object
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unsigned Offset = Fixup.getOffset();
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// Number of bytes we need to fixup
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unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
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// Used to point to big endian bytes
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unsigned FullSize;
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switch ((unsigned)Kind) {
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case FK_Data_2:
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case Mips::fixup_Mips_16:
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FullSize = 2;
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break;
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case FK_Data_8:
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case Mips::fixup_Mips_64:
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FullSize = 8;
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break;
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case FK_Data_4:
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default:
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FullSize = 4;
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break;
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}
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/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
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/// data fragment, at the offset specified by the fixup and following the
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/// fixup kind as appropriate.
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const {
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MCFixupKind Kind = Fixup.getKind();
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Value = adjustFixupValue(Fixup, Value);
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// Grab current value, if any, from bits.
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uint64_t CurVal = 0;
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if (!Value)
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return; // Doesn't change encoding.
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// Where do we start in the object
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unsigned Offset = Fixup.getOffset();
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// Number of bytes we need to fixup
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unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
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// Used to point to big endian bytes
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unsigned FullSize;
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switch ((unsigned)Kind) {
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case FK_Data_2:
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case Mips::fixup_Mips_16:
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FullSize = 2;
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break;
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case FK_Data_8:
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case Mips::fixup_Mips_64:
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FullSize = 8;
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break;
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case FK_Data_4:
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default:
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FullSize = 4;
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break;
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}
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// Grab current value, if any, from bits.
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uint64_t CurVal = 0;
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
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CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
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}
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uint64_t Mask = ((uint64_t)(-1) >>
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(64 - getFixupKindInfo(Kind).TargetSize));
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CurVal |= Value & Mask;
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// Write out the fixed up bytes back to the code/data bits.
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
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Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
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}
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
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CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
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}
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unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
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uint64_t Mask = ((uint64_t)(-1) >>
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(64 - getFixupKindInfo(Kind).TargetSize));
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CurVal |= Value & Mask;
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// MipsFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_Mips_16", 0, 16, 0 },
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{ "fixup_Mips_32", 0, 32, 0 },
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{ "fixup_Mips_REL32", 0, 32, 0 },
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{ "fixup_Mips_26", 0, 26, 0 },
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{ "fixup_Mips_HI16", 0, 16, 0 },
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{ "fixup_Mips_LO16", 0, 16, 0 },
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{ "fixup_Mips_GPREL16", 0, 16, 0 },
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{ "fixup_Mips_LITERAL", 0, 16, 0 },
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{ "fixup_Mips_GOT_Global", 0, 16, 0 },
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{ "fixup_Mips_GOT_Local", 0, 16, 0 },
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{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_CALL16", 0, 16, 0 },
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{ "fixup_Mips_GPREL32", 0, 32, 0 },
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{ "fixup_Mips_SHIFT5", 6, 5, 0 },
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{ "fixup_Mips_SHIFT6", 6, 5, 0 },
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{ "fixup_Mips_64", 0, 64, 0 },
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{ "fixup_Mips_TLSGD", 0, 16, 0 },
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{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
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{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_TLSLDM", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
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{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
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{ "fixup_Mips_GOT_PAGE", 0, 16, 0 },
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{ "fixup_Mips_GOT_OFST", 0, 16, 0 },
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{ "fixup_Mips_GOT_DISP", 0, 16, 0 },
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{ "fixup_Mips_HIGHER", 0, 16, 0 },
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{ "fixup_Mips_HIGHEST", 0, 16, 0 },
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{ "fixup_Mips_GOT_HI16", 0, 16, 0 },
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{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
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{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
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{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
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{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
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{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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// Write out the fixed up bytes back to the code/data bits.
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
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Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
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}
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}
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/// @name Target Relaxation Interfaces
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/// @{
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const MCFixupKindInfo &MipsAsmBackend::
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getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// MipsFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_Mips_16", 0, 16, 0 },
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{ "fixup_Mips_32", 0, 32, 0 },
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{ "fixup_Mips_REL32", 0, 32, 0 },
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{ "fixup_Mips_26", 0, 26, 0 },
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{ "fixup_Mips_HI16", 0, 16, 0 },
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{ "fixup_Mips_LO16", 0, 16, 0 },
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{ "fixup_Mips_GPREL16", 0, 16, 0 },
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{ "fixup_Mips_LITERAL", 0, 16, 0 },
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{ "fixup_Mips_GOT_Global", 0, 16, 0 },
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{ "fixup_Mips_GOT_Local", 0, 16, 0 },
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{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_CALL16", 0, 16, 0 },
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{ "fixup_Mips_GPREL32", 0, 32, 0 },
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{ "fixup_Mips_SHIFT5", 6, 5, 0 },
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{ "fixup_Mips_SHIFT6", 6, 5, 0 },
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{ "fixup_Mips_64", 0, 64, 0 },
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{ "fixup_Mips_TLSGD", 0, 16, 0 },
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{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
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{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_TLSLDM", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
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{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
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{ "fixup_Mips_GOT_PAGE", 0, 16, 0 },
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{ "fixup_Mips_GOT_OFST", 0, 16, 0 },
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{ "fixup_Mips_GOT_DISP", 0, 16, 0 },
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{ "fixup_Mips_HIGHER", 0, 16, 0 },
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{ "fixup_Mips_HIGHEST", 0, 16, 0 },
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{ "fixup_Mips_GOT_HI16", 0, 16, 0 },
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{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
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{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
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{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
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{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
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{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
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};
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/// MayNeedRelaxation - Check whether the given instruction may need
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/// relaxation.
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///
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/// \param Inst - The instruction to test.
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bool mayNeedRelaxation(const MCInst &Inst) const {
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return false;
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}
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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/// fixupNeedsRelaxation - Target specific predicate for whether a given
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/// fixup requires the associated instruction to be relaxed.
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const {
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// FIXME.
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assert(0 && "RelaxInstruction() unimplemented");
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return false;
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}
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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/// RelaxInstruction - Relax the instruction in the given fragment
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/// to the next wider instruction.
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///
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/// \param Inst - The instruction to relax, which may be the same
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/// as the output.
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/// \param [out] Res On return, the relaxed instruction.
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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}
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/// WriteNopData - Write an (optimal) nop sequence of Count bytes
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/// to the given output. If the target cannot generate such a sequence,
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/// it should return an error.
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///
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/// \return - True on success.
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bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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// Check for a less than instruction size number of bytes
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// FIXME: 16 bit instructions are not handled yet here.
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// We shouldn't be using a hard coded number for instruction size.
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if (Count % 4) return false;
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/// @}
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->Write32(0);
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return true;
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}
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/// WriteNopData - Write an (optimal) nop sequence of Count bytes
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/// to the given output. If the target cannot generate such a sequence,
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/// it should return an error.
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///
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/// \return - True on success.
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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// Check for a less than instruction size number of bytes
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// FIXME: 16 bit instructions are not handled yet here.
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// We shouldn't be using a hard coded number for instruction size.
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if (Count % 4) return false;
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->Write32(0);
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return true;
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}
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/// processFixupValue - Target hook to process the literal value of a fixup
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/// if necessary.
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void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCFixup &Fixup, const MCFragment *DF,
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MCValue &Target, uint64_t &Value,
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bool &IsResolved) {
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// At this point we'll ignore the value returned by adjustFixupValue as
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// we are only checking if the fixup can be applied correctly. We have
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// access to MCContext from here which allows us to report a fatal error
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// with *possibly* a source code location.
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(void)adjustFixupValue(Fixup, Value, &Asm.getContext());
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}
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}; // class MipsAsmBackend
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} // namespace
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/// processFixupValue - Target hook to process the literal value of a fixup
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/// if necessary.
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void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFixup &Fixup,
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const MCFragment *DF,
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MCValue &Target,
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uint64_t &Value,
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bool &IsResolved) {
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// At this point we'll ignore the value returned by adjustFixupValue as
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// we are only checking if the fixup can be applied correctly. We have
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// access to MCContext from here which allows us to report a fatal error
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// with *possibly* a source code location.
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(void)adjustFixupValue(Fixup, Value, &Asm.getContext());
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}
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// MCAsmBackend
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MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
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@ -341,4 +296,3 @@ MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/false, /*Is64Bit*/true);
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}
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92
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
Normal file
92
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
Normal file
@ -0,0 +1,92 @@
|
||||
//===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the MipsAsmBackend class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
|
||||
#ifndef MIPSASMBACKEND_H
|
||||
#define MIPSASMBACKEND_H
|
||||
|
||||
#include "MCTargetDesc/MipsFixupKinds.h"
|
||||
#include "llvm/MC/MCAsmBackend.h"
|
||||
#include "llvm/ADT/Triple.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MCAssembler;
|
||||
class MCFixupKindInfo;
|
||||
class Target;
|
||||
class MCObjectWriter;
|
||||
|
||||
class MipsAsmBackend : public MCAsmBackend {
|
||||
Triple::OSType OSType;
|
||||
bool IsLittle; // Big or little endian
|
||||
bool Is64Bit; // 32 or 64 bit words
|
||||
|
||||
public:
|
||||
MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle,
|
||||
bool _is64Bit)
|
||||
: MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle),
|
||||
Is64Bit(_is64Bit) {}
|
||||
|
||||
MCObjectWriter *createObjectWriter(raw_ostream &OS) const;
|
||||
|
||||
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
|
||||
uint64_t Value) const;
|
||||
|
||||
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
|
||||
|
||||
unsigned getNumFixupKinds() const {
|
||||
return Mips::NumTargetFixupKinds;
|
||||
}
|
||||
|
||||
/// @name Target Relaxation Interfaces
|
||||
/// @{
|
||||
|
||||
/// MayNeedRelaxation - Check whether the given instruction may need
|
||||
/// relaxation.
|
||||
///
|
||||
/// \param Inst - The instruction to test.
|
||||
bool mayNeedRelaxation(const MCInst &Inst) const {
|
||||
return false;
|
||||
}
|
||||
|
||||
/// fixupNeedsRelaxation - Target specific predicate for whether a given
|
||||
/// fixup requires the associated instruction to be relaxed.
|
||||
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
|
||||
const MCRelaxableFragment *DF,
|
||||
const MCAsmLayout &Layout) const {
|
||||
// FIXME.
|
||||
assert(0 && "RelaxInstruction() unimplemented");
|
||||
return false;
|
||||
}
|
||||
|
||||
/// RelaxInstruction - Relax the instruction in the given fragment
|
||||
/// to the next wider instruction.
|
||||
///
|
||||
/// \param Inst - The instruction to relax, which may be the same
|
||||
/// as the output.
|
||||
/// \param [out] Res On return, the relaxed instruction.
|
||||
void relaxInstruction(const MCInst &Inst, MCInst &Res) const {}
|
||||
|
||||
/// @}
|
||||
|
||||
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
|
||||
|
||||
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
|
||||
const MCFixup &Fixup, const MCFragment *DF,
|
||||
MCValue &Target, uint64_t &Value, bool &IsResolved);
|
||||
|
||||
}; // class MipsAsmBackend
|
||||
|
||||
} // namespace
|
||||
|
||||
#endif
|
Loading…
Reference in New Issue
Block a user