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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -69,10 +69,6 @@ class RegScavenger {
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/// available, unset means the register is currently being used.
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BitVector RegsAvailable;
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/// ImplicitDefed - If bit is set that means the register is defined by an
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/// implicit_def instructions. That means it can be clobbered at will.
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BitVector ImplicitDefed;
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/// CurrDist - Distance from MBB entry to the current instruction MBBI.
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///
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unsigned CurrDist;
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@ -117,25 +113,18 @@ public:
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bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
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bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
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bool isImplicitlyDefined(unsigned Reg) const { return ImplicitDefed[Reg]; }
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/// getRegsUsed - return all registers currently in use in used.
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void getRegsUsed(BitVector &used, bool includeReserved);
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/// setUsed / setUnused - Mark the state of one or a number of registers.
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///
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void setUsed(unsigned Reg, bool ImpDef = false);
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void setUsed(BitVector &Regs, bool ImpDef = false) {
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void setUsed(unsigned Reg);
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void setUsed(BitVector &Regs) {
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RegsAvailable &= ~Regs;
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if (ImpDef)
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ImplicitDefed |= Regs;
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else
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ImplicitDefed &= ~Regs;
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}
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void setUnused(unsigned Reg, const MachineInstr *MI);
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void setUnused(BitVector &Regs) {
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RegsAvailable |= Regs;
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ImplicitDefed &= ~Regs;
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}
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/// FindUnusedReg - Find a unused register of the specified register class
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@ -124,7 +124,9 @@ void LiveIntervals::processImplicitDefs() {
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ImpDefMIs.push_back(MI);
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continue;
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}
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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bool ChangedToImpDef = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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@ -133,16 +135,35 @@ void LiveIntervals::processImplicitDefs() {
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continue;
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if (!ImpDefRegs.count(Reg))
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continue;
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// Use is a copy, just turn it into an implicit_def.
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unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
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if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
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Reg == SrcReg) {
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bool isKill = MO.isKill();
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MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
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for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
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MI->RemoveOperand(j);
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if (isKill)
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ImpDefRegs.erase(Reg);
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ChangedToImpDef = true;
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break;
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}
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MO.setIsUndef();
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if (MO.isKill() || MI->isRegTiedToDefOperand(i))
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ImpDefRegs.erase(Reg);
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}
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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ImpDefRegs.erase(MO.getReg());
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if (ChangedToImpDef) {
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// Backtrack to process this new implicit_def.
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--I;
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} else {
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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ImpDefRegs.erase(MO.getReg());
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}
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}
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}
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@ -155,33 +176,39 @@ void LiveIntervals::processImplicitDefs() {
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continue;
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if (!ImpDefRegs.count(Reg))
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continue;
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bool HasLocalUse = false;
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for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(Reg),
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RE = mri_->reg_end(); RI != RE; ) {
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MachineOperand &RMO = RI.getOperand();
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MachineInstr *RMI = &*RI;
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++RI;
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if (RMO.isDef()) {
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// Don't expect another def of the same register.
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assert(RMI == MI &&
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"Register with multiple defs including an implicit_def?");
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continue;
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// If there are multiple defs of the same register and at least one
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// is not an implicit_def, do not insert implicit_def's before the
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// uses.
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bool Skip = false;
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for (MachineRegisterInfo::def_iterator DI = mri_->def_begin(Reg),
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DE = mri_->def_end(); DI != DE; ++DI) {
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if (DI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) {
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Skip = true;
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break;
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}
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}
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if (Skip)
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continue;
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for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
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UE = mri_->use_end(); UI != UE; ) {
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MachineOperand &RMO = UI.getOperand();
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MachineInstr *RMI = &*UI;
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++UI;
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MachineBasicBlock *RMBB = RMI->getParent();
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if (RMBB == MBB) {
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HasLocalUse = true;
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if (RMBB == MBB)
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continue;
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}
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const TargetRegisterClass* RC = mri_->getRegClass(Reg);
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unsigned NewVReg = mri_->createVirtualRegister(RC);
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BuildMI(*RMBB, RMI, RMI->getDebugLoc(),
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tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg);
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MachineInstrBuilder MIB =
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BuildMI(*RMBB, RMI, RMI->getDebugLoc(),
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tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg);
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(*MIB).getOperand(0).setIsUndef();
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RMO.setReg(NewVReg);
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RMO.setIsUndef();
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RMO.setIsKill();
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}
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if (!HasLocalUse)
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MI->eraseFromParent();
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}
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ImpDefRegs.clear();
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ImpDefMIs.clear();
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@ -57,28 +57,22 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI,
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}
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/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
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void RegScavenger::setUsed(unsigned Reg) {
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RegsAvailable.reset(Reg);
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ImplicitDefed[Reg] = ImpDef;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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unsigned SubReg = *SubRegs; ++SubRegs)
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RegsAvailable.reset(SubReg);
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ImplicitDefed[SubReg] = ImpDef;
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}
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}
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/// setUnused - Set the register and its sub-registers as being unused.
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void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
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RegsAvailable.set(Reg);
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ImplicitDefed.reset(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
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if (!RedefinesSuperRegPart(MI, Reg, TRI))
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RegsAvailable.set(SubReg);
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ImplicitDefed.reset(SubReg);
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}
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}
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void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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@ -94,7 +88,6 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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if (!MBB) {
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NumPhysRegs = TRI->getNumRegs();
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RegsAvailable.resize(NumPhysRegs);
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ImplicitDefed.resize(NumPhysRegs);
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// Create reserved registers bitvector.
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ReservedRegs = TRI->getReservedRegs(MF);
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@ -113,7 +106,6 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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ScavengeRestore = NULL;
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CurrDist = 0;
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DistanceMap.clear();
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ImplicitDefed.reset();
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// All registers started out unused.
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RegsAvailable.set();
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@ -195,7 +187,10 @@ void RegScavenger::forward() {
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ScavengeRestore = NULL;
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}
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bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
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#if 0
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if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
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return;
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#endif
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// Separate register operands into 3 classes: uses, defs, earlyclobbers.
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SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
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@ -221,14 +216,7 @@ void RegScavenger::forward() {
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assert(isUsed(Reg) && "Using an undefined register!");
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// Kill of implicit_def defined registers are ignored. e.g.
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// entry: 0x2029ab8, LLVM BB @0x1b06080, ID#0:
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// Live Ins: %R0
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// %R0<def> = IMPLICIT_DEF
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// %R0<def> = IMPLICIT_DEF
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// STR %R0<kill>, %R0, %reg0, 0, 14, %reg0, Mem:ST(4,4) [0x1b06510 + 0]
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// %R1<def> = LDR %R0, %reg0, 24, 14, %reg0, Mem:LD(4,4) [0x1b065bc + 0]
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if (MO.isKill() && !isReserved(Reg) && !isImplicitlyDefined(Reg)) {
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if (MO.isKill() && !isReserved(Reg)) {
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KillRegs.set(Reg);
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// Mark sub-registers as used.
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@ -278,10 +266,9 @@ void RegScavenger::forward() {
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// Implicit def is allowed to "re-define" any register. Similarly,
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// implicitly defined registers can be clobbered.
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assert((isReserved(Reg) || isUnused(Reg) ||
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IsImpDef || isImplicitlyDefined(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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setUsed(Reg, IsImpDef);
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setUsed(Reg);
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}
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}
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@ -2669,19 +2669,28 @@ SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
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CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
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for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
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CopyMI->RemoveOperand(i);
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CopyMI->getOperand(0).setIsUndef();
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bool NoUse = mri_->use_empty(SrcReg);
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if (NoUse) {
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for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
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E = mri_->reg_end(); I != E; ) {
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assert(I.getOperand().isDef());
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MachineInstr *DefMI = &*I;
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++I;
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for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
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RE = mri_->reg_end(); RI != RE; ) {
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assert(RI.getOperand().isDef());
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MachineInstr *DefMI = &*RI;
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++RI;
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// The implicit_def source has no other uses, delete it.
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assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
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li_->RemoveMachineInstrFromMaps(DefMI);
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DefMI->eraseFromParent();
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}
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}
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// Mark uses of implicit_def isUndef.
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for (MachineRegisterInfo::use_iterator RI = mri_->use_begin(DstReg),
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RE = mri_->use_end(); RI != RE; ++RI) {
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assert((*RI).getParent() == MBB);
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RI.getOperand().setIsUndef();
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}
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++I;
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return true;
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}
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99
test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
Normal file
99
test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
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@ -0,0 +1,99 @@
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; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
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@XX = external global i32* ; <i32**> [#uses=1]
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define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
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entry:
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br i1 undef, label %bb5, label %bb
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bb: ; preds = %bb, %entry
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br label %bb
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bb5: ; preds = %entry
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br i1 undef, label %bb6, label %bb8
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bb6: ; preds = %bb6, %bb5
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br i1 undef, label %bb8, label %bb6
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bb8: ; preds = %bb6, %bb5
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br label %bb15
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bb9: ; preds = %bb15
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br i1 undef, label %bb10, label %bb11
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bb10: ; preds = %bb9
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unreachable
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bb11: ; preds = %bb9
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br i1 undef, label %bb15, label %bb12
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bb12: ; preds = %bb11
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%0 = load i32** @XX, align 4 ; <i32*> [#uses=0]
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br label %bb228.i
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bb74.i: ; preds = %bb228.i
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br i1 undef, label %bb138.i, label %bb145.i
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bb138.i: ; preds = %bb74.i
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br label %bb145.i
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bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
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br i1 undef, label %bb146.i, label %bb151.i
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bb146.i: ; preds = %bb145.i
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br i1 undef, label %bb228.i, label %bb151.i
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bb151.i: ; preds = %bb146.i, %bb145.i
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br i1 undef, label %bb153.i, label %bb228.i
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bb153.i: ; preds = %bb151.i
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br i1 undef, label %bb220.i, label %bb.nph.i98
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bb.nph.i98: ; preds = %bb153.i
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br label %bb158.i
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bb158.i: ; preds = %bb218.i, %bb.nph.i98
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%1 = sub i32 undef, undef ; <i32> [#uses=4]
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%2 = sub i32 undef, undef ; <i32> [#uses=1]
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br i1 undef, label %bb168.i, label %bb160.i
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bb160.i: ; preds = %bb158.i
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br i1 undef, label %bb161.i, label %bb168.i
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bb161.i: ; preds = %bb160.i
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br i1 undef, label %bb168.i, label %bb163.i
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bb163.i: ; preds = %bb161.i
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br i1 undef, label %bb167.i, label %bb168.i
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bb167.i: ; preds = %bb163.i
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br label %bb168.i
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bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
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%f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; <i32> [#uses=1]
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%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
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store i32 %c.14.i, i32* undef, align 4
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store i32 undef, i32* null, align 4
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br i1 undef, label %bb211.i, label %bb218.i
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bb211.i: ; preds = %bb168.i
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br label %bb218.i
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bb218.i: ; preds = %bb211.i, %bb168.i
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br i1 undef, label %bb220.i, label %bb158.i
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bb220.i: ; preds = %bb218.i, %bb153.i
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br i1 undef, label %bb221.i, label %bb228.i
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bb221.i: ; preds = %bb220.i
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br label %bb228.i
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bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
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br i1 undef, label %bb74.i, label %bb145.i
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bb15: ; preds = %bb11, %bb8
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br i1 undef, label %return, label %bb9
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return: ; preds = %bb15
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ret void
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}
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