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Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on

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register allocation by allowing all 32 D-registers to be used. Patch by Cameron
Zwarich.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lang Hames
2012-03-15 18:49:02 +00:00
parent bcfa982c48
commit 45b5f88938
4 changed files with 29 additions and 27 deletions
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2
test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
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@@ -1,4 +1,4 @@
; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
; RUN: llc -mcpu=cortex-a8 -mattr=-neonfp < %s | FileCheck %s
; PR5423
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"

28
test/CodeGen/ARM/2010-12-07-PEIBug.ll
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@@ -4,36 +4,12 @@
define hidden void @foo() nounwind ssp {
entry:
; CHECK: foo:
; CHECK: push {r7, lr}
; CHECK-NEXT: mov r7, sp
; CHECK: mov r7, sp
; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vpush {d10, d11}
%tmp40 = load <4 x i8>* undef
%tmp41 = extractelement <4 x i8> %tmp40, i32 2
%conv42 = zext i8 %tmp41 to i32
%conv43 = sitofp i32 %conv42 to float
%div44 = fdiv float %conv43, 2.560000e+02
%vecinit45 = insertelement <4 x float> undef, float %div44, i32 2
%vecinit46 = insertelement <4 x float> %vecinit45, float 1.000000e+00, i32 3
store <4 x float> %vecinit46, <4 x float>* undef
br i1 undef, label %if.then105, label %if.else109
if.then105: ; preds = %entry
br label %if.end114
if.else109: ; preds = %entry
br label %if.end114
if.end114: ; preds = %if.else109, %if.then105
%call185 = call float @bar()
%vecinit186 = insertelement <4 x float> undef, float %call185, i32 1
%call189 = call float @bar()
%vecinit190 = insertelement <4 x float> %vecinit186, float %call189, i32 2
%vecinit191 = insertelement <4 x float> %vecinit190, float 1.000000e+00, i32 3
store <4 x float> %vecinit191, <4 x float>* undef
tail call void asm sideeffect "","~{d8},~{d10},~{d11}"() nounwind
; CHECK: vpop {d10, d11}
; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: pop {r7, pc}
ret void
}