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Use MVT instead of EVT in more instruction lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172933 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4390,7 +4390,7 @@ static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
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/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
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/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
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/// Then bitcast to their original type, ensuring they get CSE'd.
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static SDValue getOnesVector(EVT VT, bool HasInt256, SelectionDAG &DAG,
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static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
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DebugLoc dl) {
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assert(VT.isVector() && "Expected a vector type");
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@ -5100,7 +5100,7 @@ X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
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if (!Subtarget->hasFp256())
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return SDValue();
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EVT VT = Op.getValueType();
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MVT VT = Op.getValueType().getSimpleVT();
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DebugLoc dl = Op.getDebugLoc();
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assert((VT.is128BitVector() || VT.is256BitVector()) &&
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@ -5298,8 +5298,8 @@ SDValue
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X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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EVT ExtVT = VT.getVectorElementType();
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MVT VT = Op.getValueType().getSimpleVT();
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MVT ExtVT = VT.getVectorElementType();
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unsigned NumElems = Op.getNumOperands();
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// Vectors containing all zeros can be matched by pxor and xorps later
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@ -5630,7 +5630,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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// to create 256-bit vectors from two other 128-bit ones.
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static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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EVT ResVT = Op.getValueType();
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MVT ResVT = Op.getValueType().getSimpleVT();
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assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
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@ -7038,10 +7038,10 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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SDValue
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X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
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SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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MVT VT = Op.getValueType().getSimpleVT();
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DebugLoc dl = Op.getDebugLoc();
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if (!Op.getOperand(0).getValueType().is128BitVector())
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if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector())
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return SDValue();
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if (VT.getSizeInBits() == 8) {
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@ -7106,7 +7106,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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return SDValue();
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SDValue Vec = Op.getOperand(0);
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EVT VecVT = Vec.getValueType();
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MVT VecVT = Vec.getValueType().getSimpleVT();
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// If this is a 256-bit vector result, first extract the 128-bit vector and
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// then extract the element from the 128-bit vector.
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@ -7133,7 +7133,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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return Res;
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}
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EVT VT = Op.getValueType();
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MVT VT = Op.getValueType().getSimpleVT();
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DebugLoc dl = Op.getDebugLoc();
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// TODO: handle v16i8.
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if (VT.getSizeInBits() == 16) {
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@ -7146,7 +7146,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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MVT::v4i32, Vec),
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Op.getOperand(1)));
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// Transform it so it match pextrw which produces a 32-bit result.
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EVT EltVT = MVT::i32;
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MVT EltVT = MVT::i32;
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SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
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Op.getOperand(0), Op.getOperand(1));
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SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
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@ -7161,7 +7161,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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// SHUFPS the element to the lowest double word, then movss.
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int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
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EVT VVT = Op.getOperand(0).getValueType();
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MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
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SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
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DAG.getUNDEF(VVT), Mask);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
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@ -7180,7 +7180,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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// Note if the lower 64 bits of the result of the UNPCKHPD is then stored
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// to a f64mem, the whole operation is folded into a single MOVHPDmr.
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int Mask[2] = { 1, -1 };
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EVT VVT = Op.getOperand(0).getValueType();
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MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
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SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
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DAG.getUNDEF(VVT), Mask);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
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@ -7193,8 +7193,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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SDValue
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X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
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SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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EVT EltVT = VT.getVectorElementType();
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MVT VT = Op.getValueType().getSimpleVT();
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MVT EltVT = VT.getVectorElementType();
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DebugLoc dl = Op.getDebugLoc();
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SDValue N0 = Op.getOperand(0);
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@ -7247,8 +7247,8 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
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SDValue
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X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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EVT EltVT = VT.getVectorElementType();
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MVT VT = Op.getValueType().getSimpleVT();
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MVT EltVT = VT.getVectorElementType();
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DebugLoc dl = Op.getDebugLoc();
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SDValue N0 = Op.getOperand(0);
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@ -7296,7 +7296,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
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static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
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LLVMContext *Context = DAG.getContext();
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DebugLoc dl = Op.getDebugLoc();
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EVT OpVT = Op.getValueType();
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MVT OpVT = Op.getValueType().getSimpleVT();
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// If this is a 256-bit vector result, first insert into a 128-bit
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// vector and then insert into the 256-bit vector.
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