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[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -236,6 +236,12 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool processInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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// Helper function that checks if the value of a vector index is within the
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// boundaries of accepted values for each RegisterKind
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// Example: INSERT.B $w0[n], $1 => 16 > n >= 0
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bool validateMSAIndex(int Val, int RegKind);
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public:
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MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
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const MCInstrInfo &MII)
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@ -1547,6 +1553,26 @@ MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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return MatchOperand_NoMatch;
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}
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bool MipsAsmParser::validateMSAIndex(int Val, int RegKind) {
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MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
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if (Val < 0)
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return false;
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switch (Kind) {
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default:
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return false;
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case MipsOperand::Kind_MSA128BRegs:
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return Val < 16;
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case MipsOperand::Kind_MSA128HRegs:
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return Val < 8;
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case MipsOperand::Kind_MSA128WRegs:
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return Val < 4;
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case MipsOperand::Kind_MSA128DRegs:
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return Val < 2;
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}
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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int RegKind) {
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@ -1589,6 +1615,102 @@ MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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Parser.Lex(); // Eat the register identifier.
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// MSA registers may be suffixed with an index in the form of:
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// 1) Immediate expression.
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// 2) General Purpose Register.
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// Examples:
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// 1) copy_s.b $29,$w0[0]
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// 2) sld.b $w0,$w1[$1]
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if (Parser.getTok().isNot(AsmToken::LBrac))
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return MatchOperand_Success;
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MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
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Operands.push_back(MipsOperand::CreateToken("[", Parser.getTok().getLoc()));
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Parser.Lex(); // Parse the '[' token.
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if (Parser.getTok().is(AsmToken::Dollar)) {
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// This must be a GPR.
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MipsOperand *RegOp;
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SMLoc VIdx = Parser.getTok().getLoc();
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Parser.Lex(); // Parse the '$' token.
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// GPR have aliases and we must account for that. Example: $30 == $fp
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if (getLexer().getKind() == AsmToken::Integer) {
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unsigned RegNum = Parser.getTok().getIntVal();
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int Reg = matchRegisterByNumber(
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RegNum, regKindToRegClass(MipsOperand::Kind_GPR32));
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if (Reg == -1) {
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Error(VIdx, "invalid general purpose register");
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return MatchOperand_ParseFail;
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}
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RegOp = MipsOperand::CreateReg(Reg, VIdx, Parser.getTok().getLoc());
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} else if (getLexer().getKind() == AsmToken::Identifier) {
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int RegNum = -1;
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std::string RegName = Parser.getTok().getString().lower();
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RegNum = matchCPURegisterName(RegName);
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if (RegNum == -1) {
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Error(VIdx, "general purpose register expected");
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return MatchOperand_ParseFail;
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}
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RegNum = getReg(regKindToRegClass(MipsOperand::Kind_GPR32), RegNum);
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RegOp = MipsOperand::CreateReg(RegNum, VIdx, Parser.getTok().getLoc());
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} else
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return MatchOperand_ParseFail;
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RegOp->setRegKind(MipsOperand::Kind_GPR32);
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Operands.push_back(RegOp);
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Parser.Lex(); // Eat the register identifier.
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if (Parser.getTok().isNot(AsmToken::RBrac))
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return MatchOperand_ParseFail;
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Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
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Parser.Lex(); // Parse the ']' token.
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return MatchOperand_Success;
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}
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// The index must be a constant expression then.
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SMLoc VIdx = Parser.getTok().getLoc();
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const MCExpr *ImmVal;
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if (getParser().parseExpression(ImmVal))
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return MatchOperand_ParseFail;
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const MCConstantExpr *expr = dyn_cast<MCConstantExpr>(ImmVal);
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if (!expr || !validateMSAIndex((int)expr->getValue(), Kind)) {
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Error(VIdx, "invalid immediate value");
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return MatchOperand_ParseFail;
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}
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SMLoc E = Parser.getTok().getEndLoc();
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if (Parser.getTok().isNot(AsmToken::RBrac))
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return MatchOperand_ParseFail;
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bool insve = Mnemonic->getToken() == "insve.b" ||
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Mnemonic->getToken() == "insve.h" ||
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Mnemonic->getToken() == "insve.w" ||
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Mnemonic->getToken() == "insve.d";
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// The second vector index of insve instructions is always 0.
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if (insve && Operands.size() > 6) {
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if (expr->getValue() != 0) {
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Error(VIdx, "immediate value must be 0");
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return MatchOperand_ParseFail;
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}
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Operands.push_back(MipsOperand::CreateToken("0", VIdx));
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} else
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Operands.push_back(MipsOperand::CreateImm(expr, VIdx, E));
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Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
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Parser.Lex(); // Parse the ']' token.
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return MatchOperand_Success;
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}
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@ -133,6 +133,45 @@ class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
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let Inst{5-0} = minor;
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}
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class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<6> n;
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bits<5> rs;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-20} = 0b00;
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let Inst{19-16} = n{3-0};
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<6> n;
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bits<5> rs;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-19} = 0b100;
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let Inst{18-16} = n{2-0};
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<6> n;
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bits<5> rs;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-18} = 0b1100;
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let Inst{17-16} = n{1-0};
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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bits<5> imm;
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bits<5> ws;
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@ -738,9 +738,9 @@ class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
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class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
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class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
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class INSERT_B_ENC : MSA_ELM_B_FMT<0b0100, 0b011001>;
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class INSERT_H_ENC : MSA_ELM_H_FMT<0b0100, 0b011001>;
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class INSERT_W_ENC : MSA_ELM_W_FMT<0b0100, 0b011001>;
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class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
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class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
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class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
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class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
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class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
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@ -1239,13 +1239,13 @@ class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterClass RCWD> {
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}
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class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterClass RCWD, RegisterClass RCS,
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RegisterOperand ROWD, RegisterOperand ROS,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWD:$wd_in, RCS:$rs, uimm6:$n);
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n);
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string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWD:$wd_in,
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RCS:$rs,
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
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ROS:$rs,
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immZExt6:$n))];
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InstrItinClass Itinerary = itin;
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string Constraints = "$wd = $wd_in";
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@ -1964,12 +1964,12 @@ class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
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class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
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class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
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class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, MSA128B,
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GPR32>;
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class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, MSA128H,
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GPR32>;
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class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, MSA128W,
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GPR32>;
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class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
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MSA128BOpnd, GPR32Opnd>;
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class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
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MSA128HOpnd, GPR32Opnd>;
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class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
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MSA128WOpnd, GPR32Opnd>;
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class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
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MSA128W, FGR32>;
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15
test/MC/Mips/msa/test_elm_insert.s
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15
test/MC/Mips/msa/test_elm_insert.s
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@ -0,0 +1,15 @@
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
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#
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
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#
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# CHECK: insert.b $w23[3], $sp # encoding: [0x79,0x03,0xed,0xd9]
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# CHECK: insert.h $w20[2], $5 # encoding: [0x79,0x22,0x2d,0x19]
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# CHECK: insert.w $w8[2], $15 # encoding: [0x79,0x32,0x7a,0x19]
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# CHECKOBJDUMP: insert.b $w23[3], $sp
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# CHECKOBJDUMP: insert.h $w20[2], $5
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# CHECKOBJDUMP: insert.w $w8[2], $15
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insert.b $w23[3], $sp
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insert.h $w20[2], $5
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insert.w $w8[2], $15
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