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R600: Remove unecessary VREG alignment.

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Unlike SGPRs VGPRs doesn't need to be aligned.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170593 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2012-12-19 22:10:34 +00:00
parent d09d43ae53
commit 45f75be564
1 changed files with 6 additions and 6 deletions
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12
lib/Target/R600/SIRegisterInfo.td
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@ -105,15 +105,15 @@ def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
// VGPR 64-bit registers
def VGPR_64 : RegisterTuples<[low, high],
[(add (decimate VGPR_32, 2)),
(add (decimate (rotl VGPR_32, 1), 2))]>;
[(add VGPR_32),
(add (rotl VGPR_32, 1))]>;
// VGPR 128-bit registers
def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w],
[(add (decimate VGPR_32, 4)),
(add (decimate (rotl VGPR_32, 1), 4)),
(add (decimate (rotl VGPR_32, 2), 4)),
(add (decimate (rotl VGPR_32, 3), 4))]>;
[(add VGPR_32),
(add (rotl VGPR_32, 1)),
(add (rotl VGPR_32, 2)),
(add (rotl VGPR_32, 3))]>;
// Register class for all scalar registers (SGPRs + Special Registers)
def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,