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Add support for READCYCLECOUNTER in Blackfin back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78506 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -111,6 +111,9 @@ BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::CTLZ, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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// READCYCLECOUNTER needs special type legalization.
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setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
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// We don't have line number support yet.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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@ -463,6 +466,34 @@ SDValue BlackfinTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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}
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}
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void
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BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) {
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DebugLoc dl = N->getDebugLoc();
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switch (N->getOpcode()) {
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default:
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llvm_unreachable("Do not know how to custom type legalize this operation!");
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return;
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case ISD::READCYCLECOUNTER: {
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// The low part of the cycle counter is in CYCLES, the high part in
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// CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
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// CYCLES2 last.
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SDValue TheChain = N->getOperand(0);
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SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
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SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
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// Use a buildpair to merge the two 32-bit values into a 64-bit one.
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Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
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// Outgoing chain. If we were to use the chain from lo instead, it would be
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// possible to entirely eliminate the CYCLES2 read in (i32 (trunc
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// readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
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// read beyond the next CYCLES read, leading to invalid results.
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Results.push_back(hi.getValue(1));
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return;
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}
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}
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}
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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unsigned BlackfinTargetLowering::getFunctionAlignment(const Function *F) const {
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return 2;
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@ -35,6 +35,9 @@ namespace llvm {
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BlackfinTargetLowering(TargetMachine &TM);
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virtual MVT getSetCCResultType(MVT VT) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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virtual void ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG);
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int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
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@ -74,6 +74,7 @@ BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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Reserved.set(AV1S);
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Reserved.set(V);
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Reserved.set(VS);
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Reserved.set(CYCLES).set(CYCLES2);
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Reserved.set(L0);
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Reserved.set(L1);
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Reserved.set(L2);
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@ -1,11 +1,17 @@
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; RUN: llvm-as < %s | llc -march=bfin | grep cycles
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; XFAIL: *
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; ExpandIntegerResult #0: 0x181a60c: i64,ch = ReadCycleCounter 0x1104b08
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; Do not know how to expand the result of this operator!
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; RUN: llvm-as < %s | llc -march=bfin | FileCheck %s
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declare i64 @llvm.readcyclecounter()
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define i64 @foo() {
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; CHECK: cycles
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; CHECK: cycles2
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define i64 @cyc64() {
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%tmp.1 = call i64 @llvm.readcyclecounter()
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ret i64 %tmp.1
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}
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; CHECK: cycles
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define i32@cyc32() {
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%tmp.1 = call i64 @llvm.readcyclecounter()
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%s = trunc i64 %tmp.1 to i32
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ret i32 %s
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}
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