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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
Clean up some DOxygen comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170629 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -146,7 +146,7 @@ public:
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const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
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const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
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/// getOperandConstraint - Returns the value of the specific constraint if
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/// \brief Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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int getOperandConstraint(unsigned OpNum,
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MCOI::OperandConstraint Constraint) const {
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@ -158,12 +158,12 @@ public:
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return -1;
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}
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/// getOpcode - Return the opcode number for this descriptor.
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/// \brief Return the opcode number for this descriptor.
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unsigned getOpcode() const {
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return Opcode;
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}
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/// getNumOperands - Return the number of declared MachineOperands for this
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/// \brief Return the number of declared MachineOperands for this
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/// MachineInstruction. Note that variadic (isVariadic() returns true)
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/// instructions may have additional operands at the end of the list, and note
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/// that the machine instruction may include implicit register def/uses as
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@ -172,7 +172,7 @@ public:
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return NumOperands;
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}
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/// getNumDefs - Return the number of MachineOperands that are register
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/// \brief Return the number of MachineOperands that are register
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/// definitions. Register definitions always occur at the start of the
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/// machine operand list. This is the number of "outs" in the .td file,
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/// and does not include implicit defs.
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@ -180,11 +180,10 @@ public:
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return NumDefs;
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}
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/// getFlags - Return flags of this instruction.
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///
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/// \brief Return flags of this instruction.
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unsigned getFlags() const { return Flags; }
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/// isVariadic - Return true if this instruction can have a variable number of
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/// \brief Return true if this instruction can have a variable number of
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/// operands. In this case, the variable operands will be after the normal
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/// operands but before the implicit definitions and uses (if any are
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/// present).
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@ -192,35 +191,37 @@ public:
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return Flags & (1 << MCID::Variadic);
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}
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/// hasOptionalDef - Set if this instruction has an optional definition, e.g.
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/// \brief Set if this instruction has an optional definition, e.g.
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/// ARM instructions which can set condition code if 's' bit is set.
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bool hasOptionalDef() const {
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return Flags & (1 << MCID::HasOptionalDef);
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}
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/// isPseudo - Return true if this is a pseudo instruction that doesn't
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/// \brief Return true if this is a pseudo instruction that doesn't
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/// correspond to a real machine instruction.
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///
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bool isPseudo() const {
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return Flags & (1 << MCID::Pseudo);
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}
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/// \brief Return true if the instruction is a return.
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bool isReturn() const {
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return Flags & (1 << MCID::Return);
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}
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/// \brief Return true if the instruction is a call.
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bool isCall() const {
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return Flags & (1 << MCID::Call);
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}
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/// isBarrier - Returns true if the specified instruction stops control flow
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/// \brief Returns true if the specified instruction stops control flow
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/// from executing the instruction immediately following it. Examples include
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/// unconditional branches and return instructions.
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bool isBarrier() const {
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return Flags & (1 << MCID::Barrier);
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}
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/// isTerminator - Returns true if this instruction part of the terminator for
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/// \brief Returns true if this instruction part of the terminator for
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/// a basic block. Typically this is things like return and branch
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/// instructions.
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///
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@ -230,7 +231,7 @@ public:
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return Flags & (1 << MCID::Terminator);
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}
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/// isBranch - Returns true if this is a conditional, unconditional, or
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/// \brief Returns true if this is a conditional, unconditional, or
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/// indirect branch. Predicates below can be used to discriminate between
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/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
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/// get more information.
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@ -238,13 +239,13 @@ public:
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return Flags & (1 << MCID::Branch);
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}
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/// isIndirectBranch - Return true if this is an indirect branch, such as a
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/// \brief Return true if this is an indirect branch, such as a
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/// branch through a register.
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bool isIndirectBranch() const {
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return Flags & (1 << MCID::IndirectBranch);
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}
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/// isConditionalBranch - Return true if this is a branch which may fall
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/// \brief Return true if this is a branch which may fall
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/// through to the next instruction or may transfer control flow to some other
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/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
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/// information about this branch.
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@ -252,7 +253,7 @@ public:
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return isBranch() & !isBarrier() & !isIndirectBranch();
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}
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/// isUnconditionalBranch - Return true if this is a branch which always
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/// \brief Return true if this is a branch which always
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/// transfers control flow to some other block. The
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/// TargetInstrInfo::AnalyzeBranch method can be used to get more information
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/// about this branch.
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@ -260,7 +261,7 @@ public:
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return isBranch() & isBarrier() & !isIndirectBranch();
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}
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/// Return true if this is a branch or an instruction which directly
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/// \brief Return true if this is a branch or an instruction which directly
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/// writes to the program counter. Considered 'may' affect rather than
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/// 'does' affect as things like predication are not taken into account.
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bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
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@ -271,7 +272,7 @@ public:
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return hasDefOfPhysReg(MI, PC, RI);
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}
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/// isPredicable - Return true if this instruction has a predicate operand
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/// \brief Return true if this instruction has a predicate operand
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/// that controls execution. It may be set to 'always', or may be set to other
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/// values. There are various methods in TargetInstrInfo that can be used to
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/// control and modify the predicate in this instruction.
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@ -279,30 +280,28 @@ public:
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return Flags & (1 << MCID::Predicable);
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}
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/// isCompare - Return true if this instruction is a comparison.
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/// \brief Return true if this instruction is a comparison.
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bool isCompare() const {
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return Flags & (1 << MCID::Compare);
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}
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/// isMoveImmediate - Return true if this instruction is a move immediate
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/// \brief Return true if this instruction is a move immediate
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/// (including conditional moves) instruction.
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bool isMoveImmediate() const {
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return Flags & (1 << MCID::MoveImm);
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}
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/// isBitcast - Return true if this instruction is a bitcast instruction.
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///
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/// \brief Return true if this instruction is a bitcast instruction.
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bool isBitcast() const {
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return Flags & (1 << MCID::Bitcast);
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}
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/// isSelect - Return true if this is a select instruction.
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///
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/// \brief Return true if this is a select instruction.
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bool isSelect() const {
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return Flags & (1 << MCID::Select);
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}
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/// isNotDuplicable - Return true if this instruction cannot be safely
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/// \brief Return true if this instruction cannot be safely
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/// duplicated. For example, if the instruction has a unique labels attached
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/// to it, duplicating it would cause multiple definition errors.
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bool isNotDuplicable() const {
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@ -331,7 +330,7 @@ public:
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// Side Effect Analysis
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//===--------------------------------------------------------------------===//
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/// mayLoad - Return true if this instruction could possibly read memory.
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/// \brief Return true if this instruction could possibly read memory.
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/// Instructions with this flag set are not necessarily simple load
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/// instructions, they may load a value and modify it, for example.
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bool mayLoad() const {
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@ -339,7 +338,7 @@ public:
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}
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/// mayStore - Return true if this instruction could possibly modify memory.
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/// \brief Return true if this instruction could possibly modify memory.
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/// Instructions with this flag set are not necessarily simple store
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/// instructions, they may store a modified value based on their operands, or
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/// may not actually modify anything, for example.
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@ -472,8 +471,7 @@ public:
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return ImplicitUses;
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}
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/// getNumImplicitUses - Return the number of implicit uses this instruction
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/// has.
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/// \brief Return the number of implicit uses this instruction
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unsigned getNumImplicitUses() const {
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if (ImplicitUses == 0) return 0;
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unsigned i = 0;
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@ -495,8 +493,7 @@ public:
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return ImplicitDefs;
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}
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/// getNumImplicitDefs - Return the number of implicit defs this instruction
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/// has.
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/// \brief Return the number of implicit defs this instruct has.
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unsigned getNumImplicitDefs() const {
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if (ImplicitDefs == 0) return 0;
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unsigned i = 0;
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@ -504,7 +501,7 @@ public:
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return i;
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}
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/// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
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/// \brief Return true if this instruction implicitly
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/// uses the specified physical register.
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bool hasImplicitUseOfPhysReg(unsigned Reg) const {
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if (const uint16_t *ImpUses = ImplicitUses)
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@ -513,7 +510,7 @@ public:
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return false;
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}
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/// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
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/// \brief Return true if this instruction implicitly
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/// defines the specified physical register.
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bool hasImplicitDefOfPhysReg(unsigned Reg,
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const MCRegisterInfo *MRI = 0) const {
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@ -524,7 +521,7 @@ public:
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return false;
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}
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/// Return true if this instruction defines the specified physical
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/// \brief Return true if this instruction defines the specified physical
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/// register, either explicitly or implicitly.
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bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
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const MCRegisterInfo &RI) const {
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@ -535,22 +532,21 @@ public:
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return hasImplicitDefOfPhysReg(Reg, &RI);
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}
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/// getSchedClass - Return the scheduling class for this instruction. The
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/// \brief Return the scheduling class for this instruction. The
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/// scheduling class is an index into the InstrItineraryData table. This
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/// returns zero if there is no known scheduling information for the
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/// instruction.
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///
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unsigned getSchedClass() const {
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return SchedClass;
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}
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/// getSize - Return the number of bytes in the encoding of this instruction,
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/// \brief Return the number of bytes in the encoding of this instruction,
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/// or zero if the encoding size cannot be known from the opcode.
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unsigned getSize() const {
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return Size;
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}
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/// findFirstPredOperandIdx() - Find the index of the first operand in the
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/// \brief Find the index of the first operand in the
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/// operand list that is used to represent the predicate. It returns -1 if
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/// none is found.
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int findFirstPredOperandIdx() const {
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