From 463fe24f1dd5132607abb3548a2acb1849e9aa99 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Thu, 3 Nov 2011 02:04:59 +0000 Subject: [PATCH] Add support for sign-extending non-legal types in SelectSIToFP(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143603 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFastISel.cpp | 19 +++-- test/CodeGen/ARM/fast-isel-conversion.ll | 96 ++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 5 deletions(-) create mode 100644 test/CodeGen/ARM/fast-isel-conversion.ll diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 78bda6c0d3e..d1f2c7fcdd2 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -1329,16 +1329,25 @@ bool ARMFastISel::SelectSIToFP(const Instruction *I) { if (!isTypeLegal(Ty, DstVT)) return false; - // FIXME: Handle sign-extension where necessary. - if (!I->getOperand(0)->getType()->isIntegerTy(32)) + Value *Src = I->getOperand(0); + EVT SrcVT = TLI.getValueType(Src->getType(), true); + if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) return false; - unsigned Op = getRegForValue(I->getOperand(0)); - if (Op == 0) return false; + unsigned SrcReg = getRegForValue(Src); + if (SrcReg == 0) return false; + + // Handle sign-extension. + if (SrcVT == MVT::i16 || SrcVT == MVT::i8) { + EVT DestVT = MVT::i32; + unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, /*isZExt*/ false); + if (ResultReg == 0) return false; + SrcReg = ResultReg; + } // The conversion routine works on fp-reg to fp-reg and the operand above // was an integer, move it to the fp registers if possible. - unsigned FP = ARMMoveToFPReg(MVT::f32, Op); + unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg); if (FP == 0) return false; unsigned Opc; diff --git a/test/CodeGen/ARM/fast-isel-conversion.ll b/test/CodeGen/ARM/fast-isel-conversion.ll new file mode 100644 index 00000000000..14666a83528 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-conversion.ll @@ -0,0 +1,96 @@ +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB + +; Test sitofp + +define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp { +entry: +; ARM: sitofp_single_i32 +; ARM: vmov s0, r0 +; ARM: vcvt.f32.s32 s0, s0 +; THUMB: sitofp_single_i32 +; THUMB: vmov s0, r0 +; THUMB: vcvt.f32.s32 s0, s0 + %b.addr = alloca float, align 4 + %conv = sitofp i32 %a to float + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp { +entry: +; ARM: sitofp_single_i16 +; ARM: sxth r0, r0 +; ARM: vmov s0, r0 +; ARM: vcvt.f32.s32 s0, s0 +; THUMB: sitofp_single_i16 +; THUMB: sxth r0, r0 +; THUMB: vmov s0, r0 +; THUMB: vcvt.f32.s32 s0, s0 + %b.addr = alloca float, align 4 + %conv = sitofp i16 %a to float + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @sitofp_single_i8(i8 %a) nounwind ssp { +entry: +; ARM: sitofp_single_i8 +; ARM: sxtb r0, r0 +; ARM: vmov s0, r0 +; ARM: vcvt.f32.s32 s0, s0 +; THUMB: sitofp_single_i8 +; THUMB: sxtb r0, r0 +; THUMB: vmov s0, r0 +; THUMB: vcvt.f32.s32 s0, s0 + %b.addr = alloca float, align 4 + %conv = sitofp i8 %a to float + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp { +entry: +; ARM: sitofp_double_i32 +; ARM: vmov s0, r0 +; ARM: vcvt.f64.s32 d16, s0 +; THUMB: sitofp_double_i32 +; THUMB: vmov s0, r0 +; THUMB: vcvt.f64.s32 d16, s0 + %b.addr = alloca double, align 8 + %conv = sitofp i32 %a to double + store double %conv, double* %b.addr, align 8 + ret void +} + +define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp { +entry: +; ARM: sitofp_double_i16 +; ARM: sxth r0, r0 +; ARM: vmov s0, r0 +; ARM: vcvt.f64.s32 d16, s0 +; THUMB: sitofp_double_i16 +; THUMB: sxth r0, r0 +; THUMB: vmov s0, r0 +; THUMB: vcvt.f64.s32 d16, s0 + %b.addr = alloca double, align 8 + %conv = sitofp i16 %a to double + store double %conv, double* %b.addr, align 8 + ret void +} + +define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp { +entry: +; ARM: sitofp_double_i8 +; ARM: sxtb r0, r0 +; ARM: vmov s0, r0 +; ARM: vcvt.f64.s32 d16, s0 +; THUMB: sitofp_double_i8 +; THUMB: sxtb r0, r0 +; THUMB: vmov s0, r0 +; THUMB: vcvt.f64.s32 d16, s0 + %b.addr = alloca double, align 8 + %conv = sitofp i8 %a to double + store double %conv, double* %b.addr, align 8 + ret void +}