6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

Add more PPC floating-point conversion instructions

Browse Source 
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2013-04-01 17:52:07 +00:00
parent a1f4290ac9
commit 4647919784
12 changed files with 325 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

92
test/CodeGen/PowerPC/float-to-int.ll Normal file
View File

@@ -0,0 +1,92 @@
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define i64 @foo(float %a) nounwind {
%x = fptosi float %a to i64
ret i64 %x
; CHECK: @foo
; CHECK: fctidz [[REG:[0-9]+]], 1
; CHECK: stfd [[REG]],
; CHECK: ld 3,
; CHECK: blr
}
define i64 @foo2(double %a) nounwind {
%x = fptosi double %a to i64
ret i64 %x
; CHECK: @foo2
; CHECK: fctidz [[REG:[0-9]+]], 1
; CHECK: stfd [[REG]],
; CHECK: ld 3,
; CHECK: blr
}
define i64 @foo3(float %a) nounwind {
%x = fptoui float %a to i64
ret i64 %x
; CHECK: @foo3
; CHECK: fctiduz [[REG:[0-9]+]], 1
; CHECK: stfd [[REG]],
; CHECK: ld 3,
; CHECK: blr
}
define i64 @foo4(double %a) nounwind {
%x = fptoui double %a to i64
ret i64 %x
; CHECK: @foo4
; CHECK: fctiduz [[REG:[0-9]+]], 1
; CHECK: stfd [[REG]],
; CHECK: ld 3,
; CHECK: blr
}
define i32 @goo(float %a) nounwind {
%x = fptosi float %a to i32
ret i32 %x
; CHECK: @goo
; CHECK: fctiwz [[REG:[0-9]+]], 1
; CHECK: stfiwx [[REG]],
; CHECK: lwz 3,
; CHECK: blr
}
define i32 @goo2(double %a) nounwind {
%x = fptosi double %a to i32
ret i32 %x
; CHECK: @goo2
; CHECK: fctiwz [[REG:[0-9]+]], 1
; CHECK: stfiwx [[REG]],
; CHECK: lwz 3,
; CHECK: blr
}
define i32 @goo3(float %a) nounwind {
%x = fptoui float %a to i32
ret i32 %x
; CHECK: @goo3
; CHECK: fctiwuz [[REG:[0-9]+]], 1
; CHECK: stfiwx [[REG]],
; CHECK: lwz 3,
; CHECK: blr
}
define i32 @goo4(double %a) nounwind {
%x = fptoui double %a to i32
ret i32 %x
; CHECK: @goo4
; CHECK: fctiwuz [[REG:[0-9]+]], 1
; CHECK: stfiwx [[REG]],
; CHECK: lwz 3,
; CHECK: blr
}

41
test/CodeGen/PowerPC/i32-to-float.ll
View File

@@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -16,11 +17,17 @@ entry:
; CHECK: frsp 1, [[REG3]]
; CHECK: blr
; CHECK-PWR6: @foo
; CHECK-PWR6: stw 3,
; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
; CHECK-PWR6: frsp 1, [[REG2]]
; CHECK-PWR6: blr
; CHECK-A2: @foo
; CHECK-A2: stw 3,
; CHECK-A2: lfiwax [[REG:[0-9]+]],
; CHECK-A2: fcfid [[REG2:[0-9]+]], [[REG]]
; CHECK-A2: frsp 1, [[REG2]]
; CHECK-A2: fcfids 1, [[REG]]
; CHECK-A2: blr
}
@@ -36,6 +43,12 @@ entry:
; CHECK: fcfid 1, [[REG2]]
; CHECK: blr
; CHECK-PWR6: @goo
; CHECK-PWR6: stw 3,
; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
; CHECK-PWR6: fcfid 1, [[REG]]
; CHECK-PWR6: blr
; CHECK-A2: @goo
; CHECK-A2: stw 3,
; CHECK-A2: lfiwax [[REG:[0-9]+]],
@@ -43,3 +56,27 @@ entry:
; CHECK-A2: blr
}
define float @foou(i32 %a) nounwind {
entry:
%x = uitofp i32 %a to float
ret float %x
; CHECK-A2: @foou
; CHECK-A2: stw 3,
; CHECK-A2: lfiwzx [[REG:[0-9]+]],
; CHECK-A2: fcfidus 1, [[REG]]
; CHECK-A2: blr
}
define double @goou(i32 %a) nounwind {
entry:
%x = uitofp i32 %a to double
ret double %x
; CHECK-A2: @goou
; CHECK-A2: stw 3,
; CHECK-A2: lfiwzx [[REG:[0-9]+]],
; CHECK-A2: fcfidu 1, [[REG]]
; CHECK-A2: blr
}

52
test/CodeGen/PowerPC/i64-to-float.ll Normal file
View File

@@ -0,0 +1,52 @@
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define float @foo(i64 %a) nounwind {
entry:
%x = sitofp i64 %a to float
ret float %x
; CHECK: @foo
; CHECK: std 3,
; CHECK: lfd [[REG:[0-9]+]],
; CHECK: fcfids 1, [[REG]]
; CHECK: blr
}
define double @goo(i64 %a) nounwind {
entry:
%x = sitofp i64 %a to double
ret double %x
; CHECK: @goo
; CHECK: std 3,
; CHECK: lfd [[REG:[0-9]+]],
; CHECK: fcfid 1, [[REG]]
; CHECK: blr
}
define float @foou(i64 %a) nounwind {
entry:
%x = uitofp i64 %a to float
ret float %x
; CHECK: @foou
; CHECK: std 3,
; CHECK: lfd [[REG:[0-9]+]],
; CHECK: fcfidus 1, [[REG]]
; CHECK: blr
}
define double @goou(i64 %a) nounwind {
entry:
%x = uitofp i64 %a to double
ret double %x
; CHECK: @goou
; CHECK: std 3,
; CHECK: lfd [[REG:[0-9]+]],
; CHECK: fcfidu 1, [[REG]]
; CHECK: blr
}

4
test/CodeGen/PowerPC/i64_fp_round.ll
View File

@@ -1,4 +1,4 @@
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -22,6 +22,6 @@ entry:
; Also check that with -enable-unsafe-fp-math we do not get that extra
; code sequence. Simply verify that there is no "isel" present.
; RUN: llc -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE
; RUN: llc -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE
; CHECK-UNSAFE-NOT: isel

9
test/CodeGen/PowerPC/stfiwx-2.ll
View File

@@ -1,11 +1,14 @@
; This cannot be a stfiwx
; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep stb
; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep stfiwx
; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s
define void @test(float %F, i8* %P) {
%I = fptosi float %F to i32
%X = trunc i32 %I to i8
store i8 %X, i8* %P
ret void
; CHECK: fctiwz 0, 1
; CHECK: stfiwx 0, 0, 4
; CHECK: lwz 4, 12(1)
; CHECK: stb 4, 0(3)
; CHECK: blr
}