From 4658ce9c1f023ca8198add9eabc9ec466d23c8cb Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 16 Aug 2013 00:15:20 +0000 Subject: [PATCH] InstCombine: Simplify if(x!=0 && x!=-1). When both constants are positive or both constants are negative, InstCombine already simplifies comparisons like this, but when it's exactly zero and -1, the operand sorting ends up reversed and the pattern fails to match. Handle that special case. Follow up for rdar://14689217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188512 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 7 ++++++- test/Transforms/InstCombine/and2.ll | 12 ++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index b474bd84ca0..bc8506a5384 100644 --- a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -849,10 +849,15 @@ Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) { case ICmpInst::ICMP_SGT: // (X != 13 & X s> 15) -> X s> 15 return RHS; case ICmpInst::ICMP_NE: + // Special case to get the ordering right when the values wrap around + // zero. + if (LHSCst->getValue() == 0 && RHSCst->getValue() == -1) + std::swap(LHSCst, RHSCst); if (LHSCst == SubOne(RHSCst)){// (X != 13 & X != 14) -> X-13 >u 1 Constant *AddCST = ConstantExpr::getNeg(LHSCst); Value *Add = Builder->CreateAdd(Val, AddCST, Val->getName()+".off"); - return Builder->CreateICmpUGT(Add, ConstantInt::get(Add->getType(), 1)); + return Builder->CreateICmpUGT(Add, ConstantInt::get(Add->getType(), 1), + Val->getName()+".cmp"); } break; // (X != 13 & X != 15) -> no change } diff --git a/test/Transforms/InstCombine/and2.ll b/test/Transforms/InstCombine/and2.ll index 504391aa485..e88fd598300 100644 --- a/test/Transforms/InstCombine/and2.ll +++ b/test/Transforms/InstCombine/and2.ll @@ -42,3 +42,15 @@ define <4 x i32> @test5(<4 x i32> %A) { %2 = and <4 x i32> , %1 ret <4 x i32> %2 } + +; Check that we combine "if x!=0 && x!=-1" into "if x+1u>1" +define i32 @test6(i64 %x) nounwind { +; CHECK: @test6 +; CHECK-NEXT: add i64 %x, 1 +; CHECK-NEXT: icmp ugt i64 %x.off, 1 + %cmp1 = icmp ne i64 %x, -1 + %not.cmp = icmp ne i64 %x, 0 + %.cmp1 = and i1 %cmp1, %not.cmp + %land.ext = zext i1 %.cmp1 to i32 + ret i32 %land.ext +}