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Assembly parsing for 2-register sequential variant of VLD2.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-10-21 22:21:10 +00:00
parent 0ad56122e5
commit 4661d4cac3
6 changed files with 54 additions and 37 deletions
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lib/Target/ARM/Disassembler/ARMDisassembler.cpp
-6
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@@ -1959,12 +1959,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
// Second output register
switch (Inst.getOpcode()) {
case ARM::VLD2d8:
case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8_UPD:
case ARM::VLD2d16_UPD:
case ARM::VLD2d32_UPD:
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32: