6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-21 18:29:46 +00:00
Code Issues Projects Releases Wiki Activity

Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153876 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Roman Divacky 2012-04-02 15:49:30 +00:00
parent 545b962f15
commit 466958c2a0
1 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -446,7 +446,16 @@ unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
// Darwin passes everything on 4 byte boundary.
if (TM.getSubtarget<PPCSubtarget>().isDarwin())
return 4;
// FIXME SVR4 TBD
// 16byte and wider vectors are passed on 16byte boundary.
if (VectorType *VTy = dyn_cast<VectorType>(Ty))
if (VTy->getBitWidth() >= 128)
return 16;
// The rest is 8 on PPC64 and 4 on PPC32 boundary.
if (PPCSubTarget.isPPC64())
return 8;
return 4;
}