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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
Move MRI into RegAllocBase. Clean up debug output a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121599 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -84,6 +84,7 @@ protected:
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};
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};
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const TargetRegisterInfo *TRI;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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VirtRegMap *VRM;
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VirtRegMap *VRM;
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LiveIntervals *LIS;
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LiveIntervals *LIS;
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LiveUnionArray PhysReg2LiveUnion;
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LiveUnionArray PhysReg2LiveUnion;
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@ -92,12 +93,12 @@ protected:
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// query on a new live virtual register.
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// query on a new live virtual register.
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OwningArrayPtr<LiveIntervalUnion::Query> Queries;
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OwningArrayPtr<LiveIntervalUnion::Query> Queries;
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RegAllocBase(): TRI(0), VRM(0), LIS(0) {}
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RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0) {}
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virtual ~RegAllocBase() {}
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virtual ~RegAllocBase() {}
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// A RegAlloc pass should call this before allocatePhysRegs.
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// A RegAlloc pass should call this before allocatePhysRegs.
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void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
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void init(VirtRegMap &vrm, LiveIntervals &lis);
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// Get an initialized query to check interferences between lvr and preg. Note
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// Get an initialized query to check interferences between lvr and preg. Note
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// that Query::init must be called at least once for each physical register
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// that Query::init must be called at least once for each physical register
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@ -74,9 +74,6 @@ class RABasic : public MachineFunctionPass, public RegAllocBase
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{
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{
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// context
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// context
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MachineFunction *MF;
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MachineFunction *MF;
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const TargetMachine *TM;
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MachineRegisterInfo *MRI;
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BitVector ReservedRegs;
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BitVector ReservedRegs;
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// analyses
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// analyses
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@ -206,9 +203,9 @@ void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
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new(Array + r) LiveIntervalUnion(r, allocator);
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new(Array + r) LiveIntervalUnion(r, allocator);
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}
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}
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void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm,
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void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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LiveIntervals &lis) {
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TRI = &vrm.getTargetRegInfo();
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TRI = &tri;
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MRI = &vrm.getRegInfo();
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VRM = &vrm;
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VRM = &vrm;
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LIS = &lis;
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LIS = &lis;
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PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
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PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
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@ -262,13 +259,15 @@ void RegAllocBase::allocatePhysRegs() {
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// selectOrSplit requests the allocator to return an available physical
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// selectOrSplit requests the allocator to return an available physical
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// register if possible and populate a list of new live intervals that
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// register if possible and populate a list of new live intervals that
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// result from splitting.
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// result from splitting.
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DEBUG(dbgs() << "\nselectOrSplit " << MRI->getRegClass(VirtReg.reg)->getName()
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<< ':' << VirtReg << '\n');
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typedef SmallVector<LiveInterval*, 4> VirtRegVec;
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typedef SmallVector<LiveInterval*, 4> VirtRegVec;
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VirtRegVec SplitVRegs;
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VirtRegVec SplitVRegs;
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unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
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unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
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if (AvailablePhysReg) {
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if (AvailablePhysReg) {
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DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg) <<
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DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg)
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" " << VirtReg << '\n');
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<< " for " << VirtReg << '\n');
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assert(!VRM->hasPhys(VirtReg.reg) && "duplicate vreg in union");
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assert(!VRM->hasPhys(VirtReg.reg) && "duplicate vreg in union");
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VRM->assignVirt2Phys(VirtReg.reg, AvailablePhysReg);
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VRM->assignVirt2Phys(VirtReg.reg, AvailablePhysReg);
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PhysReg2LiveUnion[AvailablePhysReg].unify(VirtReg);
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PhysReg2LiveUnion[AvailablePhysReg].unify(VirtReg);
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@ -416,7 +415,6 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
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// Check for an available register in this class.
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// Check for an available register in this class.
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const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
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const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
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DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
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E = TRC->allocation_order_end(*MF);
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E = TRC->allocation_order_end(*MF);
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@ -469,14 +467,9 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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<< ((Value*)mf.getFunction())->getName() << '\n');
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<< ((Value*)mf.getFunction())->getName() << '\n');
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MF = &mf;
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MF = &mf;
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TM = &mf.getTarget();
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MRI = &mf.getRegInfo();
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DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
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DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
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const TargetRegisterInfo *TRI = TM->getRegisterInfo();
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RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
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RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
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getAnalysis<LiveIntervals>());
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ReservedRegs = TRI->getReservedRegs(*MF);
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ReservedRegs = TRI->getReservedRegs(*MF);
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@ -45,9 +45,6 @@ namespace {
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class RAGreedy : public MachineFunctionPass, public RegAllocBase {
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class RAGreedy : public MachineFunctionPass, public RegAllocBase {
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// context
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// context
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MachineFunction *MF;
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MachineFunction *MF;
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const TargetMachine *TM;
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MachineRegisterInfo *MRI;
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BitVector ReservedRegs;
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BitVector ReservedRegs;
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// analyses
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// analyses
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@ -230,11 +227,6 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
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SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands;
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SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands;
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// Check for an available register in this class.
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// Check for an available register in this class.
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DEBUG({
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const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
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dbgs() << "RegClass: " << TRC->getName() << ' ';
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});
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AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
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AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
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while (unsigned PhysReg = Order.next()) {
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while (unsigned PhysReg = Order.next()) {
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// Check interference and as a side effect, intialize queries for this
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// Check interference and as a side effect, intialize queries for this
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@ -305,12 +297,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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<< ((Value*)mf.getFunction())->getName() << '\n');
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<< ((Value*)mf.getFunction())->getName() << '\n');
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MF = &mf;
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MF = &mf;
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TM = &mf.getTarget();
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RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
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MRI = &mf.getRegInfo();
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const TargetRegisterInfo *TRI = TM->getRegisterInfo();
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RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
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getAnalysis<LiveIntervals>());
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ReservedRegs = TRI->getReservedRegs(*MF);
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ReservedRegs = TRI->getReservedRegs(*MF);
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SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
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SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
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