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[AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences.

Browse Source 
rdar://problem/20748715


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236346 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2015-05-01 20:57:11 +00:00
parent ff6f472575
commit 4688a0507c
2 changed files with 21 additions and 2 deletions
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10
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -3598,7 +3598,10 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
AArch64_AM::ASR, 31, /*WantResult=*/false);
} else {
assert(VT == MVT::i64 && "Unexpected value type.");
MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
// LHSReg and RHSReg cannot be killed by this Mul, since they are
// reused in the next instruction.
MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg,
/*IsKill=*/false);
unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
RHSReg, RHSIsKill);
emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
@ -3627,7 +3630,10 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
AArch64::sub_32);
} else {
assert(VT == MVT::i64 && "Unexpected value type.");
MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
// LHSReg and RHSReg cannot be killed by this Mul, since they are
// reused in the next instruction.
MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg,
/*IsKill=*/false);
unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
RHSReg, RHSIsKill);
emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,

13
test/CodeGen/AArch64/arm64-fast-isel.ll
View File

@ -101,3 +101,16 @@ entry:
store i32 %cond91, i32* %addr, align 4
ret void
}
define i64 @mul_umul(i64 %arg) {
; CHECK-LABEL: mul_umul:
; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
entry:
%sub.ptr.div = sdiv exact i64 %arg, 8
%tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
%tmp1 = extractvalue { i64, i1 } %tmp, 0
ret i64 %tmp1
}
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)