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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-05 13:29:22 +00:00
Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill
pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108536 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
e098e7a96d
commit
468a2a44e2
@ -22,7 +22,6 @@ set(sources
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X86COFFMachineModuleInfo.cpp
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X86ELFWriterInfo.cpp
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X86FloatingPoint.cpp
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X86FloatingPointRegKill.cpp
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X86ISelDAGToDAG.cpp
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X86ISelLowering.cpp
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X86InstrInfo.cpp
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@ -49,11 +49,6 @@ FunctionPass *createX86FloatingPointStackifierPass();
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/// crossings.
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FunctionPass *createSSEDomainFixPass();
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/// createX87FPRegKillInserterPass - This function returns a pass which
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/// inserts FP_REG_KILL instructions where needed.
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///
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FunctionPass *createX87FPRegKillInserterPass();
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/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
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/// to the specified MCE object.
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FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
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@ -622,7 +622,6 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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case X86::FP_REG_KILL:
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break;
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case X86::MOVPC32r: {
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// This emits the "call" portion of this pseudo instruction.
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@ -1,153 +0,0 @@
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//===-- X86FloatingPoint.cpp - FP_REG_KILL inserter -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the pass which inserts FP_REG_KILL instructions.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86-codegen"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Instructions.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumFPKill, "Number of FP_REG_KILL instructions added");
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namespace {
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struct FPRegKiller : public MachineFunctionPass {
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static char ID;
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FPRegKiller() : MachineFunctionPass(&ID) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "X86 FP_REG_KILL inserter";
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}
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};
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char FPRegKiller::ID = 0;
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}
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FunctionPass *llvm::createX87FPRegKillInserterPass() {
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return new FPRegKiller();
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}
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/// isFPStackVReg - Return true if the specified vreg is from a fp stack
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/// register class.
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static bool isFPStackVReg(unsigned RegNo, const MachineRegisterInfo &MRI) {
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if (!TargetRegisterInfo::isVirtualRegister(RegNo))
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return false;
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switch (MRI.getRegClass(RegNo)->getID()) {
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default: return false;
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case X86::RFP32RegClassID:
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case X86::RFP64RegClassID:
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case X86::RFP80RegClassID:
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return true;
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}
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}
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/// ContainsFPStackCode - Return true if the specific MBB has floating point
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/// stack code, and thus needs an FP_REG_KILL.
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static bool ContainsFPStackCode(MachineBasicBlock *MBB,
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const MachineRegisterInfo &MRI) {
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// Scan the block, looking for instructions that define or use fp stack vregs.
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
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if (!I->getOperand(op).isReg())
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continue;
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if (unsigned Reg = I->getOperand(op).getReg())
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if (isFPStackVReg(Reg, MRI))
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return true;
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}
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}
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// Check PHI nodes in successor blocks. These PHI's will be lowered to have
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// a copy of the input value in this block, which is a definition of the
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// value.
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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E = MBB->succ_end(); SI != E; ++ SI) {
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MachineBasicBlock *SuccBB = *SI;
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for (MachineBasicBlock::iterator I = SuccBB->begin(), E = SuccBB->end();
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I != E; ++I) {
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// All PHI nodes are at the top of the block.
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if (!I->isPHI()) break;
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if (isFPStackVReg(I->getOperand(0).getReg(), MRI))
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return true;
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}
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}
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return false;
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}
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bool FPRegKiller::runOnMachineFunction(MachineFunction &MF) {
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// If we are emitting FP stack code, scan the basic block to determine if this
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// block defines or uses any FP values. If so, put an FP_REG_KILL instruction
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// before the terminator of the block.
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// Note that FP stack instructions are used in all modes for long double,
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// so we always need to do this check.
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// Also note that it's possible for an FP stack register to be live across
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// an instruction that produces multiple basic blocks (SSE CMOV) so we
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// must check all the generated basic blocks.
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// Scan all of the machine instructions in these MBBs, checking for FP
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// stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
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// Fast-path: If nothing is using the x87 registers, we don't need to do
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// any scanning.
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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if (MRI.getRegClassVirtRegs(X86::RFP80RegisterClass).empty() &&
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MRI.getRegClassVirtRegs(X86::RFP64RegisterClass).empty() &&
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MRI.getRegClassVirtRegs(X86::RFP32RegisterClass).empty())
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return false;
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bool Changed = false;
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MachineFunction::iterator MBBI = MF.begin();
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MachineFunction::iterator EndMBB = MF.end();
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for (; MBBI != EndMBB; ++MBBI) {
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MachineBasicBlock *MBB = MBBI;
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// If this block returns, ignore it. We don't want to insert an FP_REG_KILL
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// before the return.
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if (!MBB->empty()) {
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MachineBasicBlock::iterator EndI = MBB->end();
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--EndI;
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if (EndI->getDesc().isReturn())
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continue;
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}
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// If we find any FP stack code, emit the FP_REG_KILL instruction.
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if (ContainsFPStackCode(MBB, MRI)) {
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BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc(),
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MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL));
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++NumFPKill;
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Changed = true;
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}
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}
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return Changed;
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}
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@ -108,10 +108,6 @@ let usesCustomInserter = 1 in { // Expanded after instruction selection.
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[(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
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}
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let isTerminator = 1 in
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let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
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def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>;
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// All FP Stack operations are represented with four instructions here. The
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// first three instructions, generated by the instruction selector, use "RFP32"
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// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
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@ -1664,14 +1664,6 @@ bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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return !isPredicated(MI);
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}
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// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
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static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
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const X86InstrInfo &TII) {
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if (MI->getOpcode() == X86::FP_REG_KILL)
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return false;
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return TII.isUnpredicatedTerminator(MI);
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}
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bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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@ -1688,7 +1680,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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// Working from the bottom, when we see a non-terminator instruction, we're
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// done.
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if (!isBrAnalysisUnpredicatedTerminator(I, *this))
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if (!isUnpredicatedTerminator(I))
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break;
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// A terminator that isn't a branch can't easily be handled by this
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@ -3341,7 +3333,6 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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break;
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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case X86::FP_REG_KILL:
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break;
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case X86::MOVPC32r: {
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// This emits the "call" portion of this pseudo instruction.
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@ -19,15 +19,11 @@
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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static cl::opt<bool>
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LiveX87("live-x87", cl::desc("Allow live X87 registers across blocks"));
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static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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switch (TheTriple.getOS()) {
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@ -186,10 +182,6 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
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bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Install a pass to insert x87 FP_REG_KILL instructions, as needed.
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if (!LiveX87)
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PM.add(createX87FPRegKillInserterPass());
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PM.add(createX86MaxStackAlignmentHeuristicPass());
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return false; // -print-machineinstr shouldn't print after this.
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}
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@ -1,133 +0,0 @@
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; RUN: llc < %s -march=x86 -mcpu=i686 | not grep jmp
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; check that branch folding understands FP_REG_KILL is not a branch
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target triple = "i686-pc-linux-gnu"
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%struct.FRAME.c34003a = type { float, float }
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@report_E = global i8 0 ; <i8*> [#uses=0]
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define void @main() {
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entry:
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%FRAME.31 = alloca %struct.FRAME.c34003a, align 8 ; <%struct.FRAME.c34003a*> [#uses=4]
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%tmp20 = call i32 @report__ident_int( i32 -50 ) ; <i32> [#uses=1]
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%tmp2021 = sitofp i32 %tmp20 to float ; <float> [#uses=5]
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%tmp23 = fcmp ult float %tmp2021, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
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%tmp26 = fcmp ugt float %tmp2021, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
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%bothcond = or i1 %tmp23, %tmp26 ; <i1> [#uses=1]
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br i1 %bothcond, label %bb, label %bb30
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bb: ; preds = %entry
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unwind
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bb30: ; preds = %entry
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%tmp35 = call i32 @report__ident_int( i32 50 ) ; <i32> [#uses=1]
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%tmp3536 = sitofp i32 %tmp35 to float ; <float> [#uses=4]
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%tmp38 = fcmp ult float %tmp3536, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
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%tmp44 = fcmp ugt float %tmp3536, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
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%bothcond226 = or i1 %tmp38, %tmp44 ; <i1> [#uses=1]
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br i1 %bothcond226, label %bb47, label %bb49
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bb47: ; preds = %bb30
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unwind
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bb49: ; preds = %bb30
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%tmp60 = fcmp ult float %tmp3536, %tmp2021 ; <i1> [#uses=1]
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%tmp60.not = xor i1 %tmp60, true ; <i1> [#uses=1]
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%tmp65 = fcmp olt float %tmp2021, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
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%bothcond227 = and i1 %tmp65, %tmp60.not ; <i1> [#uses=1]
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br i1 %bothcond227, label %cond_true68, label %cond_next70
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cond_true68: ; preds = %bb49
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unwind
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cond_next70: ; preds = %bb49
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%tmp71 = call i32 @report__ident_int( i32 -30 ) ; <i32> [#uses=1]
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%tmp7172 = sitofp i32 %tmp71 to float ; <float> [#uses=3]
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%tmp74 = fcmp ult float %tmp7172, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
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%tmp80 = fcmp ugt float %tmp7172, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
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%bothcond228 = or i1 %tmp74, %tmp80 ; <i1> [#uses=1]
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br i1 %bothcond228, label %bb83, label %bb85
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bb83: ; preds = %cond_next70
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unwind
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bb85: ; preds = %cond_next70
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%tmp90 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 1 ; <float*> [#uses=3]
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store float %tmp7172, float* %tmp90
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%tmp92 = call i32 @report__ident_int( i32 30 ) ; <i32> [#uses=1]
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%tmp9293 = sitofp i32 %tmp92 to float ; <float> [#uses=7]
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%tmp95 = fcmp ult float %tmp9293, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
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%tmp101 = fcmp ugt float %tmp9293, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
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%bothcond229 = or i1 %tmp95, %tmp101 ; <i1> [#uses=1]
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br i1 %bothcond229, label %bb104, label %bb106
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bb104: ; preds = %bb85
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unwind
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bb106: ; preds = %bb85
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%tmp111 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 0 ; <float*> [#uses=2]
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store float %tmp9293, float* %tmp111
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%tmp123 = load float* %tmp90 ; <float> [#uses=4]
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%tmp125 = fcmp ult float %tmp9293, %tmp123 ; <i1> [#uses=1]
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br i1 %tmp125, label %cond_next147, label %cond_true128
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cond_true128: ; preds = %bb106
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%tmp133 = fcmp olt float %tmp123, %tmp2021 ; <i1> [#uses=1]
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%tmp142 = fcmp ogt float %tmp9293, %tmp3536 ; <i1> [#uses=1]
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%bothcond230 = or i1 %tmp133, %tmp142 ; <i1> [#uses=1]
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br i1 %bothcond230, label %bb145, label %cond_next147
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bb145: ; preds = %cond_true128
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unwind
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cond_next147: ; preds = %cond_true128, %bb106
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%tmp157 = fcmp ugt float %tmp123, -3.000000e+01 ; <i1> [#uses=1]
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%tmp165 = fcmp ult float %tmp9293, -3.000000e+01 ; <i1> [#uses=1]
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%bothcond231 = or i1 %tmp157, %tmp165 ; <i1> [#uses=1]
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br i1 %bothcond231, label %bb168, label %bb169
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bb168: ; preds = %cond_next147
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unwind
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bb169: ; preds = %cond_next147
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%tmp176 = fcmp ugt float %tmp123, 3.000000e+01 ; <i1> [#uses=1]
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%tmp184 = fcmp ult float %tmp9293, 3.000000e+01 ; <i1> [#uses=1]
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%bothcond232 = or i1 %tmp176, %tmp184 ; <i1> [#uses=1]
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br i1 %bothcond232, label %bb187, label %bb188
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bb187: ; preds = %bb169
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unwind
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bb188: ; preds = %bb169
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%tmp192 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 3.000000e+01 ) ; <float> [#uses=2]
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%tmp194 = load float* %tmp90 ; <float> [#uses=1]
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%tmp196 = fcmp ugt float %tmp194, 0.000000e+00 ; <i1> [#uses=1]
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br i1 %tmp196, label %bb207, label %cond_next200
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cond_next200: ; preds = %bb188
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%tmp202 = load float* %tmp111 ; <float> [#uses=1]
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%tmp204 = fcmp ult float %tmp202, 0.000000e+00 ; <i1> [#uses=1]
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br i1 %tmp204, label %bb207, label %bb208
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bb207: ; preds = %cond_next200, %bb188
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unwind
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bb208: ; preds = %cond_next200
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%tmp212 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 0.000000e+00 ) ; <float> [#uses=1]
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%tmp214 = fcmp oge float %tmp212, %tmp192 ; <i1> [#uses=1]
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%tmp217 = fcmp oge float %tmp192, 1.000000e+02 ; <i1> [#uses=1]
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%tmp221 = or i1 %tmp214, %tmp217 ; <i1> [#uses=1]
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br i1 %tmp221, label %cond_true224, label %UnifiedReturnBlock
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cond_true224: ; preds = %bb208
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call void @abort( ) noreturn
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ret void
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UnifiedReturnBlock: ; preds = %bb208
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ret void
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}
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declare fastcc float @c34003a__ident.154(%struct.FRAME.c34003a* %CHAIN.32, float %x)
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declare i32 @report__ident_int(i32 %x)
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declare void @abort() noreturn
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