6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-18 13:34:04 +00:00
Code Issues Projects Releases Wiki Activity

Rename CreateTLOF->createTLOF to match the rest of the file and the

Browse Source 
rest of the targets with a similar function name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209926 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-05-30 22:47:48 +00:00
parent 94141a42ed
commit 46949d58b9
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -50,7 +50,7 @@ cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
// FIXME: Remove this once the bug has been fixed!
extern cl::opt<bool> ANDIGlueBug;
static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
static TargetLoweringObjectFile *createTLOF(const PPCTargetMachine &TM) {
if (TM.getSubtargetImpl()->isDarwin())
return new TargetLoweringObjectFileMachO();
@ -61,7 +61,7 @@ static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
}
PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
: TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
: TargetLowering(TM, createTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
setPow2DivIsCheap();
@ -7930,8 +7930,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
DCI.AddToWorklist(RV.getNode());
RV = DAGCombineFastRecip(RV, DCI);
if (RV.getNode()) {
// Unfortunately, RV is now NaN if the input was exactly 0. Select out
// this case and force the answer to 0.
// Unfortunately, RV is now NaN if the input was exactly 0. Select out
// this case and force the answer to 0.
EVT VT = RV.getValueType();