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Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-10-14 23:58:49 +00:00
parent 5d79859f66
commit 46995fa7e2
2 changed files with 25 additions and 0 deletions
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8
lib/Target/ARM/ARMISelLowering.cpp
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@ -4057,6 +4057,14 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
// A shuffle can only come from building a vector from various
// elements of other vectors.
return SDValue();
} else if (V.getOperand(0).getValueType().getVectorElementType() !=
VT.getVectorElementType()) {
// This code doesn't know how to handle shuffles where the vector
// element types do not match (this happens because type legalization
// promotes the return type of EXTRACT_VECTOR_ELT).
// FIXME: It might be appropriate to extend this code to handle
// mismatched types.
return SDValue();
}
// Record this extraction against the appropriate vector if possible...

17
test/CodeGen/ARM/vext.ll
View File

@ -133,3 +133,20 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
ret <8 x i16> %tmp3
}
; PR11129
; Make sure this doesn't crash
define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
; CHECK: test_elem_mismatch:
; CHECK: vstr.64
%tmp0 = load <2 x i64>* %src, align 16
%tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
%tmp2 = extractelement <4 x i32> %tmp1, i32 0
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
%tmp4 = trunc i32 %tmp2 to i16
%tmp5 = trunc i32 %tmp3 to i16
%tmp6 = insertelement <4 x i16> undef, i16 %tmp4, i32 0
%tmp7 = insertelement <4 x i16> %tmp6, i16 %tmp5, i32 1
store <4 x i16> %tmp7, <4 x i16>* %dest, align 4
ret void
}