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[x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201767 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -158,6 +158,7 @@ class TA { Map OpMap = TA; }
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class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
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class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
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class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
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class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
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class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
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class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
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class OBXS { Prefix OpPrefix = XS; }
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class PS : TB { Prefix OpPrefix = PS; }
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class PS : TB { Prefix OpPrefix = PS; }
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class PD : TB { Prefix OpPrefix = PD; }
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class PD : TB { Prefix OpPrefix = PD; }
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class XD : TB { Prefix OpPrefix = XD; }
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class XD : TB { Prefix OpPrefix = XD; }
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@ -3728,7 +3728,7 @@ def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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// was introduced with SSE2, it's backward compatible.
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// was introduced with SSE2, it's backward compatible.
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def PAUSE : I<0x90, RawFrm, (outs), (ins),
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def PAUSE : I<0x90, RawFrm, (outs), (ins),
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"pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
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"pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
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REP, Requires<[HasSSE2]>;
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OBXS, Requires<[HasSSE2]>;
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// Load, store, and memory fence
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// Load, store, and memory fence
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def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
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def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
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@ -203,7 +203,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
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HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
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HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
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HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
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HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
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HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
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HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
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HasREPPrefix = Rec->getValueAsBit("hasREPPrefix");
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IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
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IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
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ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
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ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
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@ -433,7 +432,7 @@ InstructionContext RecognizableInstr::insnContext() const {
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insnContext = IC_ADSIZE;
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insnContext = IC_ADSIZE;
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else if (OpPrefix == X86Local::XD)
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else if (OpPrefix == X86Local::XD)
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insnContext = IC_XD;
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insnContext = IC_XD;
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else if (OpPrefix == X86Local::XS || HasREPPrefix)
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else if (OpPrefix == X86Local::XS)
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insnContext = IC_XS;
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insnContext = IC_XS;
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else
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else
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insnContext = IC;
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insnContext = IC;
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@ -74,8 +74,6 @@ private:
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bool HasEVEX_KZ;
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bool HasEVEX_KZ;
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/// The hasEVEX_B field from the record
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/// The hasEVEX_B field from the record
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bool HasEVEX_B;
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bool HasEVEX_B;
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/// The hasREPPrefix field from the record
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bool HasREPPrefix;
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/// The isCodeGenOnly field from the record
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/// The isCodeGenOnly field from the record
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bool IsCodeGenOnly;
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bool IsCodeGenOnly;
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/// The ForceDisassemble field from the record
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/// The ForceDisassemble field from the record
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