From 46b53c9e4ba6fb9700f8af2e12da6266fb651bc0 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 17 Oct 2014 17:42:56 +0000 Subject: [PATCH] R600/SI: Remove SI_BUFFER_RSRC pseudo Just use REG_SEQUENCE directly, so there are fewer instructions to need to deal with later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220056 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 29 +++++++++++++++++++------ lib/Target/R600/SIISelLowering.cpp | 30 -------------------------- lib/Target/R600/SIInstructions.td | 6 ------ test/CodeGen/R600/smrd.ll | 2 +- 4 files changed, 24 insertions(+), 43 deletions(-) diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index c7539716597..8a9340289d8 100644 --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -944,21 +944,38 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, return SelectMUBUFAddr64(Addr, SRsrc, VAddr, Offset); } +static SDValue buildSMovImm32(SelectionDAG *DAG, SDLoc DL, uint64_t Val) { + SDValue K = DAG->getTargetConstant(Val, MVT::i32); + return SDValue(DAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0); +} + static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) { SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr); SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); - if (RsrcDword1) + if (RsrcDword1) { PtrHi = SDValue(DAG->getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi, DAG->getConstant(RsrcDword1, MVT::i32)), 0); + } - SDValue DataLo = DAG->getTargetConstant( - RsrcDword2And3 & APInt::getAllOnesValue(32).getZExtValue(), MVT::i32); - SDValue DataHi = DAG->getTargetConstant(RsrcDword2And3 >> 32, MVT::i32); + SDValue DataLo = buildSMovImm32(DAG, DL, + RsrcDword2And3 & UINT64_C(0xFFFFFFFF)); + SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32); - const SDValue Ops[] = { PtrLo, PtrHi, DataLo, DataHi }; - return SDValue(DAG->getMachineNode(AMDGPU::SI_BUFFER_RSRC, DL, + const SDValue Ops[] = { + DAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32), + PtrLo, + DAG->getTargetConstant(AMDGPU::sub0, MVT::i32), + PtrHi, + DAG->getTargetConstant(AMDGPU::sub1, MVT::i32), + DataLo, + DAG->getTargetConstant(AMDGPU::sub2, MVT::i32), + DataHi, + DAG->getTargetConstant(AMDGPU::sub3, MVT::i32) + }; + + return SDValue(DAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops), 0); } diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 28881955156..dc9153d3e91 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -623,36 +623,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( MI->eraseFromParent(); break; } - case AMDGPU::SI_BUFFER_RSRC: { - unsigned SuperReg = MI->getOperand(0).getReg(); - unsigned Args[4]; - for (unsigned i = 0, e = 4; i < e; ++i) { - MachineOperand &Arg = MI->getOperand(i + 1); - - if (Arg.isReg()) { - Args[i] = Arg.getReg(); - continue; - } - - assert(Arg.isImm()); - unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), Reg) - .addImm(Arg.getImm()); - Args[i] = Reg; - } - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), - SuperReg) - .addReg(Args[0]) - .addImm(AMDGPU::sub0) - .addReg(Args[1]) - .addImm(AMDGPU::sub1) - .addReg(Args[2]) - .addImm(AMDGPU::sub2) - .addReg(Args[3]) - .addImm(AMDGPU::sub3); - MI->eraseFromParent(); - break; - } case AMDGPU::V_SUB_F64: { unsigned DestReg = MI->getOperand(0).getReg(); BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg) diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 1b94c2b9c5a..6e4321d7c67 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1794,12 +1794,6 @@ def SI_ADDR64_RSRC : InstSI < "", [] >; -def SI_BUFFER_RSRC : InstSI < - (outs SReg_128:$srsrc), - (ins SReg_32:$ptr_lo, SReg_32:$ptr_hi, SSrc_32:$data_lo, SSrc_32:$data_hi), - "", [] ->; - def V_SUB_F64 : InstSI < (outs VReg_64:$dst), (ins VReg_64:$src0, VReg_64:$src1), diff --git a/test/CodeGen/R600/smrd.ll b/test/CodeGen/R600/smrd.ll index 329739142e2..d18e4fa3f53 100644 --- a/test/CodeGen/R600/smrd.ll +++ b/test/CodeGen/R600/smrd.ll @@ -37,8 +37,8 @@ entry: ; SMRD load with a 64-bit offset ; CHECK-LABEL: {{^}}smrd3: -; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0 ; CHECK-DAG: S_MOV_B32 s[[SHI:[0-9]+]], 4 +; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0 ; ; FIXME: We don't need to copy these values to VGPRs ; CHECK-DAG: V_MOV_B32_e32 v[[VLO:[0-9]+]], s[[SLO]] ; CHECK-DAG: V_MOV_B32_e32 v[[VHI:[0-9]+]], s[[SHI]]