Update the X86 disassembler to use xacquire and xrelease when appropriate.

This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.

Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease.  Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.

rdar://11019859


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184490 91177308-0d34-0410-b5e6-96231b3b80d8

test/MC/Disassembler/X86/simple-tests.txt

@@ -764,7 +764,35 @@
 # CHECK: repne
 # CHECK-NEXT: movb  $0, (%rax)
 0xf2 0xc6 0x0 0x0
-# CHECK: rep
+
+# rdar://11019859 Support 2013 Haswell RTM instructions and HLE prefixes
+# CHECK: xrelease
 # CHECK-NEXT: lock
 # CHECK-NEXT: incl   (%rax)
 0xf3 0xf0 0xff 0x00
+
+# CHECK: xrelease
+# CHECK-NEXT: xchgl %ebx, %eax
+0xf3 0x93
+# CHECK: xrelease
+# CHECK-NEXT: xchgl %ebx, (%rax)
+0xf3 0x87 0x18
+# CHECK: xrelease
+# CHECK-NEXT: movb %al, (%rbx)
+0xf3 0x88 0x03
+# CHECK: xrelease
+# CHECK-NEXT: movl %eax, (%rbx)
+0xf3 0x89 0x03
+# CHECK: xrelease
+# CHECK-NEXT: movb $1, (%rbx)
+0xf3 0xc6 0x03 0x01
+# CHECK: xrelease
+# CHECK-NEXT: movl $1, (%rbx)
+0xf3 0xc7 0x03 0x01 0x00 0x00 0x00
+
+# CHECK: xacquire
+# CHECK-NEXT: xchgl %ebx, %eax
+0xf2 0x93
+# CHECK: xacquire
+# CHECK-NEXT: xchgl %ebx, (%rax)
+0xf2 0x87 0x18