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Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -141,6 +141,10 @@ void RegScavenger::forward() {
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// Find out which registers are early clobbered, killed, defined, and marked
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// def-dead in this instruction.
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// FIXME: The scavenger is not predication aware. If the instruction is
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// predicated, conservatively assume "kill" markers do not actually kill the
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// register. Similarly ignores "dead" markers.
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bool isPred = TII->isPredicated(MI);
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BitVector EarlyClobberRegs(NumPhysRegs);
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BitVector KillRegs(NumPhysRegs);
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BitVector DefRegs(NumPhysRegs);
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@@ -155,11 +159,11 @@ void RegScavenger::forward() {
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if (MO.isUse()) {
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// Two-address operands implicitly kill.
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if (MO.isKill() || MI->isRegTiedToDefOperand(i))
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if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i)))
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addRegWithSubRegs(KillRegs, Reg);
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} else {
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assert(MO.isDef());
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if (MO.isDead())
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if (!isPred && MO.isDead())
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addRegWithSubRegs(DeadRegs, Reg);
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else
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addRegWithSubRegs(DefRegs, Reg);
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