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ARM: fix CPS decoding when ambiguous with QADD

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Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS decoding as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amaury de la Vieuville
2013-06-08 13:38:52 +00:00
parent c64835b0c5
commit 46e136c952
4 changed files with 47 additions and 0 deletions
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4
test/MC/Disassembler/ARM/basic-arm-instructions.txt
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@@ -454,10 +454,14 @@
# CHECK: cpsie aif
# CHECK: cps #15
# CHECK: cpsid if, #10
# CHECK: cpsid af, #17
# CHECK: cpsie f, #26
0xc0 0x01 0x08 0xf1
0x0f 0x00 0x02 0xf1
0xca 0x00 0x0e 0xf1
0x51 0x01 0x0e 0xf1
0x5a 0x00 0x0a 0xf1
#------------------------------------------------------------------------------

9
test/MC/Disassembler/ARM/invalid-CPS-arm.txt Normal file
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@@ -0,0 +1,9 @@
# CPS: various encodings that are ambiguous with other instructions
# RUN: echo "0x9f 0xff 0x4e 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
# RUN: echo "0x80 0x80 0x2c 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
# RUN: echo "0xce 0x3f 0x28 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
# RUN: echo "0x80 0x00 0x20 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
# RUN: echo "0xa0 0x00 0x00 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
# CHECK: invalid instruction encoding