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Fix PR4753.
When undoing a reuse in ReuseInfo::GetRegForReload, check if it was only a sub-register being used. The MachineOperand::getSubReg() method is only valid for virtual registers, so we have to recover the sub-register index manually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79855 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
072a56e37d
commit
46ff969ca6
@ -810,6 +810,21 @@ unsigned ReuseInfo::GetRegForReload(const TargetRegisterClass *RC,
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ReusedOp NewOp = Op;
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ReusedOp NewOp = Op;
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Reuses.erase(Reuses.begin()+ro);
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Reuses.erase(Reuses.begin()+ro);
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// MI may be using only a sub-register of PhysRegUsed.
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unsigned RealPhysRegUsed = MI->getOperand(NewOp.Operand).getReg();
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unsigned SubIdx = 0;
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assert(TargetRegisterInfo::isPhysicalRegister(RealPhysRegUsed) &&
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"A reuse cannot be a virtual register");
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if (PRRU != RealPhysRegUsed) {
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// What was the sub-register index?
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unsigned SubReg;
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for (SubIdx = 1; (SubReg = TRI->getSubReg(PRRU, SubIdx)); SubIdx++)
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if (SubReg == RealPhysRegUsed)
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break;
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assert(SubReg == RealPhysRegUsed &&
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"Operand physreg is not a sub-register of PhysRegUsed");
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}
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// Ok, we're going to try to reload the assigned physreg into the
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// Ok, we're going to try to reload the assigned physreg into the
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// slot that we were supposed to in the first place. However, that
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// slot that we were supposed to in the first place. However, that
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// register could hold a reuse. Check to see if it conflicts or
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// register could hold a reuse. Check to see if it conflicts or
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@ -842,7 +857,6 @@ unsigned ReuseInfo::GetRegForReload(const TargetRegisterClass *RC,
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Spills.ClobberPhysReg(NewPhysReg);
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Spills.ClobberPhysReg(NewPhysReg);
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Spills.ClobberPhysReg(NewOp.PhysRegReused);
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Spills.ClobberPhysReg(NewOp.PhysRegReused);
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unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg();
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unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg;
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unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg;
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MI->getOperand(NewOp.Operand).setReg(RReg);
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MI->getOperand(NewOp.Operand).setReg(RReg);
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MI->getOperand(NewOp.Operand).setSubReg(0);
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MI->getOperand(NewOp.Operand).setSubReg(0);
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69
test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
Normal file
69
test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
Normal file
@ -0,0 +1,69 @@
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; RUN: llvm-as < %s | llc -march=x86
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; PR4753
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; This function has a sub-register reuse undone.
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@uint8 = external global i32 ; <i32*> [#uses=3]
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declare signext i8 @foo(i32, i8 signext) nounwind readnone
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declare signext i8 @bar(i32, i8 signext) nounwind readnone
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define i32 @uint80(i8 signext %p_52) nounwind {
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entry:
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%0 = sext i8 %p_52 to i16 ; <i16> [#uses=1]
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%1 = tail call i32 @func_24(i16 zeroext %0, i8 signext ptrtoint (i8 (i32, i8)* @foo to i8)) nounwind; <i32> [#uses=1]
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%2 = trunc i32 %1 to i8 ; <i8> [#uses=1]
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%3 = or i8 %2, 1 ; <i8> [#uses=1]
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%4 = tail call i32 @safe(i32 1) nounwind ; <i32> [#uses=0]
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%5 = tail call i32 @func_24(i16 zeroext 0, i8 signext undef) nounwind; <i32> [#uses=1]
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%6 = trunc i32 %5 to i8 ; <i8> [#uses=1]
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%7 = xor i8 %3, %p_52 ; <i8> [#uses=1]
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%8 = xor i8 %7, %6 ; <i8> [#uses=1]
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%9 = icmp ne i8 %p_52, 0 ; <i1> [#uses=1]
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%10 = zext i1 %9 to i8 ; <i8> [#uses=1]
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%11 = tail call i32 @func_24(i16 zeroext ptrtoint (i8 (i32, i8)* @bar to i16), i8 signext %10) nounwind; <i32> [#uses=1]
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%12 = tail call i32 @func_24(i16 zeroext 0, i8 signext 1) nounwind; <i32> [#uses=0]
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br i1 undef, label %bb2, label %bb
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bb: ; preds = %entry
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br i1 undef, label %bb2, label %bb3
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bb2: ; preds = %bb, %entry
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br label %bb3
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bb3: ; preds = %bb2, %bb
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%iftmp.2.0 = phi i32 [ 0, %bb2 ], [ 1, %bb ] ; <i32> [#uses=1]
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%13 = icmp ne i32 %11, %iftmp.2.0 ; <i1> [#uses=1]
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%14 = tail call i32 @safe(i32 -2) nounwind ; <i32> [#uses=0]
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%15 = zext i1 %13 to i8 ; <i8> [#uses=1]
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%16 = tail call signext i8 @func_53(i8 signext undef, i8 signext 1, i8 signext %15, i8 signext %8) nounwind; <i8> [#uses=0]
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br i1 undef, label %bb5, label %bb4
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bb4: ; preds = %bb3
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%17 = volatile load i32* @uint8, align 4 ; <i32> [#uses=0]
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br label %bb5
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bb5: ; preds = %bb4, %bb3
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%18 = volatile load i32* @uint8, align 4 ; <i32> [#uses=0]
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%19 = sext i8 undef to i16 ; <i16> [#uses=1]
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%20 = tail call i32 @func_24(i16 zeroext %19, i8 signext 1) nounwind; <i32> [#uses=0]
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br i1 undef, label %return, label %bb6.preheader
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bb6.preheader: ; preds = %bb5
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%21 = sext i8 %p_52 to i32 ; <i32> [#uses=1]
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%22 = volatile load i32* @uint8, align 4 ; <i32> [#uses=0]
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%23 = tail call i32 (...)* @safefuncts(i32 %21, i32 1) nounwind; <i32> [#uses=0]
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unreachable
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return: ; preds = %bb5
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ret i32 undef
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}
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declare i32 @func_24(i16 zeroext, i8 signext)
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declare i32 @safe(i32)
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declare signext i8 @func_53(i8 signext, i8 signext, i8 signext, i8 signext)
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declare i32 @safefuncts(...)
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