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https://github.com/c64scene-ar/llvm-6502.git
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Eliminate spurious empty space; make code easier to page through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15146 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
1245c35935
commit
4722544855
@ -441,8 +441,7 @@ unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
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/// is okay to use as an immediate argument to a certain binary operator.
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///
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/// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
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bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator)
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{
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bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
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ConstantSInt *Op1Cs;
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ConstantUInt *Op1Cu;
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@ -795,8 +794,7 @@ void ISel::SelectPHINodes() {
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// We already inserted an initialization of the register for this
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// predecessor. Recycle it.
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ValReg = EntryIt->second;
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} else {
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} else {
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// Get the incoming value into a virtual register.
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//
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Value *Val = PN->getIncomingValue(i);
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@ -815,11 +813,11 @@ void ISel::SelectPHINodes() {
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// might be arbitrarily complex if it is a constant expression),
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// just insert the computation at the top of the basic block.
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MachineBasicBlock::iterator PI = PredMBB->begin();
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// Skip over any PHI nodes though!
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while (PI != PredMBB->end() && PI->getOpcode() == PPC32::PHI)
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++PI;
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ValReg = getReg(Val, PredMBB, PI);
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}
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@ -918,7 +916,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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const Type *CompTy = Op0->getType();
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unsigned Class = getClassB(CompTy);
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unsigned Op0r = getReg(Op0, MBB, IP);
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// Use crand for lt, gt and crandc for le, ge
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unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC32::CRAND : PPC32::CRANDC;
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// ? cr1[lt] : cr1[gt]
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@ -951,7 +949,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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unsigned HiLow = makeAnotherReg(Type::IntTy);
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unsigned HiTmp = makeAnotherReg(Type::IntTy);
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unsigned FinalTmp = makeAnotherReg(Type::IntTy);
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BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r+1)
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.addImm(LowCst & 0xFFFF);
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BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow)
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@ -965,7 +963,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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} else {
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unsigned ConstReg = makeAnotherReg(CompTy);
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copyConstantToRegister(MBB, IP, CI, ConstReg);
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// cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
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BuildMI(*MBB, IP, Opcode, 2, PPC32::CR0).addReg(Op0r)
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.addReg(ConstReg);
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@ -1029,9 +1027,9 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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unsigned DestReg = getReg(I);
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unsigned OpNum = I.getOpcode();
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const Type *Ty = I.getOperand (0)->getType();
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EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
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unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -1108,14 +1106,11 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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// to get the register of the Cond value
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if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
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// We successfully folded the setcc into the select instruction.
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
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IP);
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OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
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Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
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} else {
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unsigned CondReg = getReg(Cond, MBB, IP);
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BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(CondReg).addSImm(0);
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Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
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}
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@ -1209,7 +1204,6 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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// Make sure we have the register number for this value...
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unsigned Reg = Val ? getReg(Val) : VR.Reg;
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switch (getClassB(Ty)) {
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case cByte:
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// Extend value into target register (8->32)
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@ -2886,11 +2880,8 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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}
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}
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// Do some statistical accounting
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if (ops.empty())
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++GEPConsts;
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if (anyCombined)
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++GEPSplits;
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if (ops.empty()) ++GEPConsts;
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if (anyCombined) ++GEPSplits;
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// Emit instructions for all the collapsed ops
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for(std::vector<CollapsedGepOp *>::iterator cgo_i = ops.begin(),
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@ -441,8 +441,7 @@ unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
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/// is okay to use as an immediate argument to a certain binary operator.
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///
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/// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
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bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator)
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{
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bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
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ConstantSInt *Op1Cs;
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ConstantUInt *Op1Cu;
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@ -795,8 +794,7 @@ void ISel::SelectPHINodes() {
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// We already inserted an initialization of the register for this
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// predecessor. Recycle it.
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ValReg = EntryIt->second;
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} else {
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} else {
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// Get the incoming value into a virtual register.
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//
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Value *Val = PN->getIncomingValue(i);
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@ -815,11 +813,11 @@ void ISel::SelectPHINodes() {
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// might be arbitrarily complex if it is a constant expression),
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// just insert the computation at the top of the basic block.
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MachineBasicBlock::iterator PI = PredMBB->begin();
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// Skip over any PHI nodes though!
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while (PI != PredMBB->end() && PI->getOpcode() == PPC32::PHI)
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++PI;
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ValReg = getReg(Val, PredMBB, PI);
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}
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@ -918,7 +916,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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const Type *CompTy = Op0->getType();
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unsigned Class = getClassB(CompTy);
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unsigned Op0r = getReg(Op0, MBB, IP);
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// Use crand for lt, gt and crandc for le, ge
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unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC32::CRAND : PPC32::CRANDC;
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// ? cr1[lt] : cr1[gt]
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@ -951,7 +949,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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unsigned HiLow = makeAnotherReg(Type::IntTy);
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unsigned HiTmp = makeAnotherReg(Type::IntTy);
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unsigned FinalTmp = makeAnotherReg(Type::IntTy);
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BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r+1)
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.addImm(LowCst & 0xFFFF);
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BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow)
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@ -965,7 +963,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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} else {
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unsigned ConstReg = makeAnotherReg(CompTy);
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copyConstantToRegister(MBB, IP, CI, ConstReg);
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// cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
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BuildMI(*MBB, IP, Opcode, 2, PPC32::CR0).addReg(Op0r)
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.addReg(ConstReg);
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@ -1029,9 +1027,9 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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unsigned DestReg = getReg(I);
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unsigned OpNum = I.getOpcode();
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const Type *Ty = I.getOperand (0)->getType();
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EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
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unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -1108,14 +1106,11 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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// to get the register of the Cond value
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if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
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// We successfully folded the setcc into the select instruction.
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
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IP);
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OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
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Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
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} else {
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unsigned CondReg = getReg(Cond, MBB, IP);
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BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(CondReg).addSImm(0);
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Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
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}
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@ -1209,7 +1204,6 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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// Make sure we have the register number for this value...
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unsigned Reg = Val ? getReg(Val) : VR.Reg;
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switch (getClassB(Ty)) {
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case cByte:
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// Extend value into target register (8->32)
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@ -2886,11 +2880,8 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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}
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}
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// Do some statistical accounting
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if (ops.empty())
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++GEPConsts;
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if (anyCombined)
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++GEPSplits;
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if (ops.empty()) ++GEPConsts;
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if (anyCombined) ++GEPSplits;
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// Emit instructions for all the collapsed ops
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for(std::vector<CollapsedGepOp *>::iterator cgo_i = ops.begin(),
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