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[x86] Kill gratuitous X86_{32,64}TargetMachine subclasses, use X86TargetMachine

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198720 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Woodhouse 2014-01-08 00:08:50 +00:00
parent b56c57bcbb
commit 476136e951
4 changed files with 29 additions and 106 deletions
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6
lib/Target/X86/X86Subtarget.cpp
View File

@ -551,14 +551,14 @@ void X86Subtarget::initializeEnvironment() {
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, const std::string &FS,
unsigned StackAlignOverride, bool is64Bit) unsigned StackAlignOverride)
: X86GenSubtargetInfo(TT, CPU, FS) : X86GenSubtargetInfo(TT, CPU, FS)
, X86ProcFamily(Others) , X86ProcFamily(Others)
, PICStyle(PICStyles::None) , PICStyle(PICStyles::None)
, TargetTriple(TT) , TargetTriple(TT)
, StackAlignOverride(StackAlignOverride) , StackAlignOverride(StackAlignOverride)
, In64BitMode(is64Bit) , In64BitMode(TargetTriple.getArch() == Triple::x86_64)
, In32BitMode(!is64Bit) , In32BitMode(TargetTriple.getArch() == Triple::x86)
, In16BitMode(false) { , In16BitMode(false) {
initializeEnvironment(); initializeEnvironment();
resetSubtargetFeatures(CPU, FS); resetSubtargetFeatures(CPU, FS);

2
lib/Target/X86/X86Subtarget.h
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@ -220,7 +220,7 @@ public:
/// ///
X86Subtarget(const std::string &TT, const std::string &CPU, X86Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, const std::string &FS,
unsigned StackAlignOverride, bool is64Bit); unsigned StackAlignOverride);
/// getStackAlignment - Returns the minimum alignment known to hold of the /// getStackAlignment - Returns the minimum alignment known to hold of the
/// stack frame on entry to the function and which must be maintained by every /// stack frame on entry to the function and which must be maintained by every

51
lib/Target/X86/X86TargetMachine.cpp
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@ -24,11 +24,11 @@ using namespace llvm;
extern "C" void LLVMInitializeX86Target() { extern "C" void LLVMInitializeX86Target() {
// Register the target. // Register the target.
RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target); RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target); RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
} }
void X86_32TargetMachine::anchor() { } void X86TargetMachine::anchor() { }
static std::string computeDataLayout(const X86Subtarget &ST) { static std::string computeDataLayout(const X86Subtarget &ST) {
// X86 is little endian // X86 is little endian
@ -69,49 +69,22 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
return Ret; return Ret;
} }
X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
DL(computeDataLayout(*getSubtargetImpl())),
InstrInfo(*this),
TLInfo(*this),
TSInfo(*this),
JITInfo(*this) {
initAsmInfo();
}
void X86_64TargetMachine::anchor() { }
X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
// The x32 ABI dictates the ILP32 programming model for x64.
DL(computeDataLayout(*getSubtargetImpl())),
InstrInfo(*this),
TLInfo(*this),
TSInfo(*this),
JITInfo(*this) {
initAsmInfo();
}
/// X86TargetMachine ctor - Create an X86 target. /// X86TargetMachine ctor - Create an X86 target.
/// ///
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, CodeGenOpt::Level OL)
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit), Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
FrameLowering(*this, Subtarget), FrameLowering(*this, Subtarget),
InstrItins(Subtarget.getInstrItineraryData()){ InstrItins(Subtarget.getInstrItineraryData()),
DL(computeDataLayout(*getSubtargetImpl())),
InstrInfo(*this),
TLInfo(*this),
TSInfo(*this),
JITInfo(*this) {
// Determine the PICStyle based on the target selected. // Determine the PICStyle based on the target selected.
if (getRelocationModel() == Reloc::Static) { if (getRelocationModel() == Reloc::Static) {
// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
@ -135,6 +108,8 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
// default to hard float ABI // default to hard float ABI
if (Options.FloatABIType == FloatABI::Default) if (Options.FloatABIType == FloatABI::Default)
this->Options.FloatABIType = FloatABI::Hard; this->Options.FloatABIType = FloatABI::Hard;
initAsmInfo();
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

76
lib/Target/X86/X86TargetMachine.h
View File

@ -30,32 +30,38 @@ namespace llvm {
class StringRef; class StringRef;
class X86TargetMachine : public LLVMTargetMachine { class X86TargetMachine : public LLVMTargetMachine {
virtual void anchor();
X86Subtarget Subtarget; X86Subtarget Subtarget;
X86FrameLowering FrameLowering; X86FrameLowering FrameLowering;
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
const DataLayout DL; // Calculates type size & alignment
X86InstrInfo InstrInfo;
X86TargetLowering TLInfo;
X86SelectionDAGInfo TSInfo;
X86JITInfo JITInfo;
public: public:
X86TargetMachine(const Target &T, StringRef TT, X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, CodeGenOpt::Level OL);
bool is64Bit);
virtual const DataLayout *getDataLayout() const { return &DL; }
virtual const X86InstrInfo *getInstrInfo() const { virtual const X86InstrInfo *getInstrInfo() const {
llvm_unreachable("getInstrInfo not implemented"); return &InstrInfo;
} }
virtual const TargetFrameLowering *getFrameLowering() const { virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering; return &FrameLowering;
} }
virtual X86JITInfo *getJITInfo() { virtual X86JITInfo *getJITInfo() {
llvm_unreachable("getJITInfo not implemented"); return &JITInfo;
} }
virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; } virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; }
virtual const X86TargetLowering *getTargetLowering() const { virtual const X86TargetLowering *getTargetLowering() const {
llvm_unreachable("getTargetLowering not implemented"); return &TLInfo;
} }
virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const { virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
llvm_unreachable("getSelectionDAGInfo not implemented"); return &TSInfo;
} }
virtual const X86RegisterInfo *getRegisterInfo() const { virtual const X86RegisterInfo *getRegisterInfo() const {
return &getInstrInfo()->getRegisterInfo(); return &getInstrInfo()->getRegisterInfo();
@ -74,64 +80,6 @@ public:
JITCodeEmitter &JCE); JITCodeEmitter &JCE);
}; };
/// X86_32TargetMachine - X86 32-bit target machine.
///
class X86_32TargetMachine : public X86TargetMachine {
virtual void anchor();
const DataLayout DL; // Calculates type size & alignment
X86InstrInfo InstrInfo;
X86TargetLowering TLInfo;
X86SelectionDAGInfo TSInfo;
X86JITInfo JITInfo;
public:
X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const DataLayout *getDataLayout() const { return &DL; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;
}
virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
return &TSInfo;
}
virtual const X86InstrInfo *getInstrInfo() const {
return &InstrInfo;
}
virtual X86JITInfo *getJITInfo() {
return &JITInfo;
}
};
/// X86_64TargetMachine - X86 64-bit target machine.
///
class X86_64TargetMachine : public X86TargetMachine {
virtual void anchor();
const DataLayout DL; // Calculates type size & alignment
X86InstrInfo InstrInfo;
X86TargetLowering TLInfo;
X86SelectionDAGInfo TSInfo;
X86JITInfo JITInfo;
public:
X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const DataLayout *getDataLayout() const { return &DL; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;
}
virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
return &TSInfo;
}
virtual const X86InstrInfo *getInstrInfo() const {
return &InstrInfo;
}
virtual X86JITInfo *getJITInfo() {
return &JITInfo;
}
};
} // End llvm namespace } // End llvm namespace
#endif #endif