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R600: Add support for v4i32 stores on Cayman
Tested-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188518 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1808,6 +1808,7 @@ class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> :
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def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>;
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def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
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def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
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class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
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: VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
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@ -31,6 +31,20 @@ entry:
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ret void
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}
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; EG-CHECK: @store_v4i32
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; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM-CHECK: @store_v4i32
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; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
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; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; SI-CHECK: @store_v4i32
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; SI-CHECK: BUFFER_STORE_DWORDX4
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define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(1)* %out
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ret void
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}
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; The stores in this function are combined by the optimizer to create a
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; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
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; should not try to split the 64-bit store back into 2 32-bit stores.
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=NI-CHECK %s
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; RUN: not llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
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; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
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; NI-CHECK: @vtx_fetch32
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; NI-CHECK: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00
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