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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
[ARM] Fix Tag_ABI_HardFP_use build attribute
Fix Tag_ABI_HardFP_use build attribute to handle single precision FP, replace deprecated Tag_ABI_HardFP_use value of 3 with 0 and also add some tests for Tag_ABI_VFP_args. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193856 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
parent
e14fb07357
commit
479a2de32a
@ -692,11 +692,15 @@ void ARMAsmPrinter::emitAttributes() {
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ATS.emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
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ATS.emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
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// ABI_HardFP_use attribute to indicate single precision FP.
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if (Subtarget->isFPOnlySP())
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ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
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ARMBuildAttrs::HardFPSinglePrecision);
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// Hard float. Use both S and D registers and conform to AAPCS-VFP.
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if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
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ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
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ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
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}
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if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
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ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
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// FIXME: Should we signal R9 usage?
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if (Subtarget->hasDivide()) {
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@ -137,8 +137,12 @@ namespace ARMBuildAttrs {
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AllowIEE754 = 3, // this code to use all the IEEE 754-defined FP encodings
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// Tag_ABI_HardFP_use, (=27), uleb128
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HardFPImplied = 0, // FP use should be implied by Tag_FP_arch
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HardFPSinglePrecision = 1, // Single-precision only
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HardFPImplied = 3, // FP use should be implied by Tag_FP_arch
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// Tag_ABI_VFP_args, (=28), uleb128
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BaseAAPCS = 0,
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HardFPAAPCS = 1,
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// Tag_DIV_use, (=44), uleb128
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AllowDIVIfExists = 0, // Allow hardware divide if available in arch, or no info exists.
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@ -12,10 +12,12 @@
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; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON
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; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON
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; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=CORTEX-A9
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15
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; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
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; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CORTEX-M4
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; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
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; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD
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; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
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; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
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; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
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@ -24,6 +26,8 @@
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; V6: .eabi_attribute 8, 1
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; V6: .eabi_attribute 24, 1
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; V6: .eabi_attribute 25, 1
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; V6-NOT: .eabi_attribute 27
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; V6-NOT: .eabi_attribute 28
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; V6M: .eabi_attribute 6, 12
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; V6M: .eabi_attribute 7, 77
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@ -31,6 +35,8 @@
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; V6M: .eabi_attribute 9, 1
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; V6M: .eabi_attribute 24, 1
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; V6M: .eabi_attribute 25, 1
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; V6M-NOT: .eabi_attribute 27
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; V6M-NOT: .eabi_attribute 28
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; ARM1156T2F-S: .cpu arm1156t2f-s
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; ARM1156T2F-S: .eabi_attribute 6, 8
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@ -42,6 +48,8 @@
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; ARM1156T2F-S: .eabi_attribute 23, 3
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; ARM1156T2F-S: .eabi_attribute 24, 1
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; ARM1156T2F-S: .eabi_attribute 25, 1
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; ARM1156T2F-S-NOT: .eabi_attribute 27
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; ARM1156T2F-S-NOT: .eabi_attribute 28
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; V7M: .eabi_attribute 6, 10
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; V7M: .eabi_attribute 7, 77
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@ -49,6 +57,8 @@
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; V7M: .eabi_attribute 9, 2
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; V7M: .eabi_attribute 24, 1
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; V7M: .eabi_attribute 25, 1
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; V7M-NOT: .eabi_attribute 27
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; V7M-NOT: .eabi_attribute 28
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; V7M: .eabi_attribute 44, 0
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; V7: .syntax unified
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@ -58,6 +68,8 @@
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; V7: .eabi_attribute 23, 3
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; V7: .eabi_attribute 24, 1
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; V7: .eabi_attribute 25, 1
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; V7-NOT: .eabi_attribute 27
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; V7-NOT: .eabi_attribute 28
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; V8: .syntax unified
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; V8: .eabi_attribute 6, 14
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@ -84,17 +96,33 @@
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; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8
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; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3
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; CORTEX-A9: .cpu cortex-a9
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; CORTEX-A9: .eabi_attribute 6, 10
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; CORTEX-A9: .eabi_attribute 7, 65
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; CORTEX-A9: .eabi_attribute 8, 1
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; CORTEX-A9: .eabi_attribute 9, 2
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; CORTEX-A9: .fpu neon
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; CORTEX-A9: .eabi_attribute 20, 1
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; CORTEX-A9: .eabi_attribute 21, 1
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; CORTEX-A9: .eabi_attribute 23, 3
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; CORTEX-A9: .eabi_attribute 24, 1
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; CORTEX-A9: .eabi_attribute 25, 1
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; CORTEX-A9-SOFT: .cpu cortex-a9
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; CORTEX-A9-SOFT: .eabi_attribute 6, 10
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; CORTEX-A9-SOFT: .eabi_attribute 7, 65
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; CORTEX-A9-SOFT: .eabi_attribute 8, 1
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; CORTEX-A9-SOFT: .eabi_attribute 9, 2
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; CORTEX-A9-SOFT: .fpu neon
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; CORTEX-A9-SOFT: .eabi_attribute 20, 1
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; CORTEX-A9-SOFT: .eabi_attribute 21, 1
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; CORTEX-A9-SOFT: .eabi_attribute 23, 3
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; CORTEX-A9-SOFT: .eabi_attribute 24, 1
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; CORTEX-A9-SOFT: .eabi_attribute 25, 1
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; CORTEX-A9-SOFT-NOT: .eabi_attribute 27
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; CORTEX-A9-SOFT-NOT: .eabi_attribute 28
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; CORTEX-A9-HARD: .cpu cortex-a9
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; CORTEX-A9-HARD: .eabi_attribute 6, 10
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; CORTEX-A9-HARD: .eabi_attribute 7, 65
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; CORTEX-A9-HARD: .eabi_attribute 8, 1
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; CORTEX-A9-HARD: .eabi_attribute 9, 2
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; CORTEX-A9-HARD: .fpu neon
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; CORTEX-A9-HARD: .eabi_attribute 20, 1
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; CORTEX-A9-HARD: .eabi_attribute 21, 1
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; CORTEX-A9-HARD: .eabi_attribute 23, 3
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; CORTEX-A9-HARD: .eabi_attribute 24, 1
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; CORTEX-A9-HARD: .eabi_attribute 25, 1
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; CORTEX-A9-HARD-NOT: .eabi_attribute 27
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; CORTEX-A9-HARD: .eabi_attribute 28, 1
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; CORTEX-A15: .cpu cortex-a15
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; CORTEX-A15: .eabi_attribute 6, 10
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@ -108,6 +136,8 @@
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; CORTEX-A15: .eabi_attribute 24, 1
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; CORTEX-A15: .eabi_attribute 25, 1
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; CORTEX-A15: .eabi_attribute 44, 2
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; CORTEX-A15-NOT: .eabi_attribute 27
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; CORTEX-A15-NOT: .eabi_attribute 28
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; CORTEX-M0: .cpu cortex-m0
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; CORTEX-M0: .eabi_attribute 6, 12
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@ -116,19 +146,38 @@
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; CORTEX-M0: .eabi_attribute 9, 1
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; CORTEX-M0: .eabi_attribute 24, 1
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; CORTEX-M0: .eabi_attribute 25, 1
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; CORTEX-M0-NOT: .eabi_attribute 27
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; CORTEX-M0-NOT: .eabi_attribute 28
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; CORTEX-M4: .cpu cortex-m4
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; CORTEX-M4: .eabi_attribute 6, 13
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; CORTEX-M4: .eabi_attribute 7, 77
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; CORTEX-M4: .eabi_attribute 8, 0
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; CORTEX-M4: .eabi_attribute 9, 2
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; CORTEX-M4: .fpu vfpv4-d16
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; CORTEX-M4: .eabi_attribute 20, 1
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; CORTEX-M4: .eabi_attribute 21, 1
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; CORTEX-M4: .eabi_attribute 23, 3
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; CORTEX-M4: .eabi_attribute 24, 1
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; CORTEX-M4: .eabi_attribute 25, 1
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; CORTEX-M4: .eabi_attribute 44, 0
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; CORTEX-M4-SOFT: .cpu cortex-m4
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; CORTEX-M4-SOFT: .eabi_attribute 6, 13
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; CORTEX-M4-SOFT: .eabi_attribute 7, 77
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; CORTEX-M4-SOFT: .eabi_attribute 8, 0
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; CORTEX-M4-SOFT: .eabi_attribute 9, 2
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; CORTEX-M4-SOFT: .fpu vfpv4-d16
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; CORTEX-M4-SOFT: .eabi_attribute 20, 1
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; CORTEX-M4-SOFT: .eabi_attribute 21, 1
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; CORTEX-M4-SOFT: .eabi_attribute 23, 3
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; CORTEX-M4-SOFT: .eabi_attribute 24, 1
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; CORTEX-M4-SOFT: .eabi_attribute 25, 1
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; CORTEX-M4-SOFT: .eabi_attribute 27, 1
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; CORTEX-M4-SOFT-NOT: .eabi_attribute 28
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; CORTEX-M4-SOFT: .eabi_attribute 44, 0
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; CORTEX-M4-HARD: .cpu cortex-m4
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; CORTEX-M4-HARD: .eabi_attribute 6, 13
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; CORTEX-M4-HARD: .eabi_attribute 7, 77
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; CORTEX-M4-HARD: .eabi_attribute 8, 0
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; CORTEX-M4-HARD: .eabi_attribute 9, 2
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; CORTEX-M4-HARD: .fpu vfpv4-d16
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; CORTEX-M4-HARD: .eabi_attribute 20, 1
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; CORTEX-M4-HARD: .eabi_attribute 21, 1
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; CORTEX-M4-HARD: .eabi_attribute 23, 3
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; CORTEX-M4-HARD: .eabi_attribute 24, 1
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; CORTEX-M4-HARD: .eabi_attribute 25, 1
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; CORTEX-M4-HARD: .eabi_attribute 27, 1
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; CORTEX-M4-HARD: .eabi_attribute 28, 1
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; CORTEX-M4-HARD: .eabi_attribute 44, 0
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; CORTEX-R5: .cpu cortex-r5
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; CORTEX-R5: .eabi_attribute 6, 10
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@ -141,6 +190,8 @@
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; CORTEX-R5: .eabi_attribute 23, 3
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; CORTEX-R5: .eabi_attribute 24, 1
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; CORTEX-R5: .eabi_attribute 25, 1
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; CORTEX-R5: .eabi_attribute 27, 1
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; CORTEX-R5-NOT: .eabi_attribute 28
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; CORTEX-R5: .eabi_attribute 44, 2
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; CORTEX-A53: .cpu cortex-a53
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@ -152,6 +203,8 @@
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; CORTEX-A53: .eabi_attribute 12, 3
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; CORTEX-A53: .eabi_attribute 24, 1
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; CORTEX-A53: .eabi_attribute 25, 1
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; CORTEX-A53-NOT: .eabi_attribute 27
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; CORTEX-A53-NOT: .eabi_attribute 28
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; CORTEX-A53: .eabi_attribute 44, 2
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; CORTEX-A57: .cpu cortex-a57
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@ -163,6 +216,8 @@
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; CORTEX-A57: .eabi_attribute 12, 3
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; CORTEX-A57: .eabi_attribute 24, 1
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; CORTEX-A57: .eabi_attribute 25, 1
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; CORTEX-A57-NOT: .eabi_attribute 27
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; CORTEX-A57-NOT: .eabi_attribute 28
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; CORTEX-A57: .eabi_attribute 44, 2
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define i32 @f(i64 %z) {
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@ -228,16 +228,16 @@
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; CORTEX-M4-NEXT: ]
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; CORTEX-M4-NEXT: Address: 0x0
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; CORTEX-M4-NEXT: Offset: 0x38
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; CORTEX-M4-NEXT: Size: 49
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; CORTEX-M4-NEXT: Size: 51
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; CORTEX-M4-NEXT: Link: 0
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; CORTEX-M4-NEXT: Info: 0
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; CORTEX-M4-NEXT: AddressAlignment: 1
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; CORTEX-M4-NEXT: EntrySize: 0
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; CORTEX-M4-NEXT: SectionData (
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; CORTEX-M4-NEXT: 0000: 41300000 00616561 62690001 26000000
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; CORTEX-M4-NEXT: 0000: 41320000 00616561 62690001 28000000
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; CORTEX-M4-NEXT: 0010: 05434F52 5445582D 4D340006 0D074D08
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; CORTEX-M4-NEXT: 0020: 0009020A 06140115 01170318 0119012C
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; CORTEX-M4-NEXT: 0030: 00
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; CORTEX-M4-NEXT: 0020: 0009020A 06140115 01170318 0119011B
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; CORTEX-M4-NEXT: 0030: 012C00
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; CORTEX-M4-NEXT: )
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; CORTEX-R5: Name: .ARM.attributes
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@ -246,16 +246,16 @@
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; CORTEX-R5-NEXT: ]
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; CORTEX-R5-NEXT: Address: 0x0
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; CORTEX-R5-NEXT: Offset: 0x3C
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; CORTEX-R5-NEXT: Size: 49
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; CORTEX-R5-NEXT: Size: 51
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; CORTEX-R5-NEXT: Link: 0
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; CORTEX-R5-NEXT: Info: 0
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; CORTEX-R5-NEXT: AddressAlignment: 1
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; CORTEX-R5-NEXT: EntrySize: 0
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; CORTEX-R5-NEXT: SectionData (
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; CORTEX-R5-NEXT: 0000: 41300000 00616561 62690001 26000000
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; CORTEX-R5-NEXT: 0000: 41320000 00616561 62690001 28000000
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; CORTEX-R5-NEXT: 0010: 05434F52 5445582D 52350006 0A075208
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; CORTEX-R5-NEXT: 0020: 0109020A 04140115 01170318 0119012C
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; CORTEX-R5-NEXT: 0030: 02
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; CORTEX-R5-NEXT: 0020: 0109020A 04140115 01170318 0119011B
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; CORTEX-R5-NEXT: 0030: 012C02
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; CORTEX-R5-NEXT: )
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define i32 @f(i64 %z) {
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