From 47ac0f0c7c39289f5970688154e385be22b7f293 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Wed, 11 Feb 2009 04:27:20 +0000 Subject: [PATCH] When scheduling a block in parts, keep track of the overall instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAG.h | 17 +++------ include/llvm/CodeGen/SchedulerRegistry.h | 24 ++++++------ include/llvm/CodeGen/SelectionDAGISel.h | 4 +- lib/CodeGen/PostRASchedulerList.cpp | 38 ++++++++++++++----- lib/CodeGen/ScheduleDAG.cpp | 17 +++------ lib/CodeGen/ScheduleDAGEmit.cpp | 6 +-- lib/CodeGen/ScheduleDAGInstrs.cpp | 19 ++++++++-- lib/CodeGen/ScheduleDAGInstrs.h | 13 +++++++ lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 3 +- lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp | 4 +- .../SelectionDAG/ScheduleDAGRRList.cpp | 8 ++-- .../SelectionDAG/ScheduleDAGSDNodes.cpp | 8 ++++ lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h | 7 ++++ .../SelectionDAG/ScheduleDAGSDNodesEmit.cpp | 16 ++++---- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 12 +++--- 15 files changed, 124 insertions(+), 72 deletions(-) diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 786a5f40738..38b437bdf01 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -31,7 +31,6 @@ namespace llvm { class MachineInstr; class TargetRegisterInfo; class ScheduleDAG; - class SelectionDAG; class SDNode; class TargetInstrInfo; class TargetInstrDesc; @@ -426,10 +425,8 @@ namespace llvm { class ScheduleDAG { public: - SelectionDAG *DAG; // DAG of the current basic block - MachineBasicBlock *BB; // Current basic block - MachineBasicBlock::iterator Begin; // The beginning of the range to be scheduled. - MachineBasicBlock::iterator End; // The end of the range to be scheduled. + MachineBasicBlock *BB; // The block in which to insert instructions. + MachineBasicBlock::iterator InsertPos;// The position to insert instructions. const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information const TargetRegisterInfo *TRI; // Target processor register info @@ -452,12 +449,6 @@ namespace llvm { /// void viewGraph(); - /// Run - perform scheduling. - /// - void Run(SelectionDAG *DAG, MachineBasicBlock *MBB, - MachineBasicBlock::iterator Begin, - MachineBasicBlock::iterator End); - /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock /// according to the order specified in Sequence. /// @@ -482,6 +473,10 @@ namespace llvm { #endif protected: + /// Run - perform scheduling. + /// + void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos); + /// BuildSchedGraph - Build SUnits and set up their Preds and Succs /// to form the scheduling dependency graph. /// diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h index b4daa05203c..c967bfc446c 100644 --- a/include/llvm/CodeGen/SchedulerRegistry.h +++ b/include/llvm/CodeGen/SchedulerRegistry.h @@ -26,13 +26,13 @@ namespace llvm { //===----------------------------------------------------------------------===// class SelectionDAGISel; -class ScheduleDAG; +class ScheduleDAGSDNodes; class SelectionDAG; class MachineBasicBlock; class RegisterScheduler : public MachinePassRegistryNode { public: - typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, bool); + typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool); static MachinePassRegistry Registry; @@ -63,28 +63,28 @@ public: /// createBURRListDAGScheduler - This creates a bottom up register usage /// reduction list scheduler. -ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, + bool Fast); /// createTDRRListDAGScheduler - This creates a top down register usage /// reduction list scheduler. -ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS, + bool Fast); /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. -ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS, + bool Fast); /// createFastDAGScheduler - This creates a "fast" scheduler. /// -ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS, + bool Fast); /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. -ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, + bool Fast); } // end namespace llvm diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 468f1b74c5e..e6bf8d76f47 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -35,7 +35,7 @@ namespace llvm { class FunctionLoweringInfo; class ScheduleHazardRecognizer; class GCFunctionInfo; - class ScheduleDAG; + class ScheduleDAGSDNodes; /// SelectionDAGISel - This is the common base class used for SelectionDAG-based /// pattern-matching instruction selectors. @@ -133,7 +133,7 @@ private: /// via the SchedulerRegistry, use it, otherwise select the /// one preferred by the target. /// - ScheduleDAG *CreateScheduler(); + ScheduleDAGSDNodes *CreateScheduler(); }; } diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index fd7135f3627..b6521e1cc00 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -139,7 +139,7 @@ namespace { /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. /// - void Observe(MachineInstr *MI); + void Observe(MachineInstr *MI, unsigned Count); /// FinishBlock - Clean up register live-range state. /// @@ -254,19 +254,26 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { // Schedule each sequence of instructions not interrupted by a label // or anything else that effectively needs to shut down scheduling. MachineBasicBlock::iterator Current = MBB->end(); + unsigned Count = MBB->size(), CurrentCount = Count; for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) { MachineInstr *MI = prior(I); if (isSchedulingBoundary(MI, Fn)) { if (I != Current) { - Scheduler.Run(0, MBB, I, Current); + Scheduler.Run(MBB, I, Current, CurrentCount); Scheduler.EmitSchedule(); } - Scheduler.Observe(MI); + Scheduler.Observe(MI, Count); Current = MI; + CurrentCount = Count - 1; } I = MI; + --Count; + } + assert(Count == 0 && "Instruction count mismatch!"); + if (MBB->begin() != Current) { + assert(CurrentCount != 0 && "Instruction count mismatch!"); + Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount); } - Scheduler.Run(0, MBB, MBB->begin(), Current); Scheduler.EmitSchedule(); // Clean up register live-range state. @@ -311,7 +318,7 @@ void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) { else // In a non-return block, examine the live-in regs of all successors. for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), - SE = BB->succ_end(); SI != SE; ++SI) + SE = BB->succ_end(); SI != SE; ++SI) for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), E = (*SI)->livein_end(); I != E; ++I) { unsigned Reg = *I; @@ -384,9 +391,9 @@ void SchedulePostRATDList::Schedule() { /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. /// -void SchedulePostRATDList::Observe(MachineInstr *MI) { +void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) { PrescanInstruction(MI); - ScanInstruction(MI, 0); + ScanInstruction(MI, Count); } /// FinishBlock - Clean up register live-range state. @@ -484,6 +491,9 @@ void SchedulePostRATDList::ScanInstruction(MachineInstr *MI, DefIndices[Reg] = Count; KillIndices[Reg] = ~0u; + assert(((KillIndices[Reg] == ~0u) != + (DefIndices[Reg] == ~0u)) && + "Kill and Def maps aren't consistent for Reg!"); Classes[Reg] = 0; RegRefs.erase(Reg); // Repeat, for all subregs. @@ -525,6 +535,9 @@ void SchedulePostRATDList::ScanInstruction(MachineInstr *MI, if (KillIndices[Reg] == ~0u) { KillIndices[Reg] = Count; DefIndices[Reg] = ~0u; + assert(((KillIndices[Reg] == ~0u) != + (DefIndices[Reg] == ~0u)) && + "Kill and Def maps aren't consistent for Reg!"); } // Repeat, for all aliases. for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { @@ -608,8 +621,8 @@ bool SchedulePostRATDList::BreakAntiDependencies() { // instructions from the bottom up, tracking information about liveness // as we go to help determine which registers are available. bool Changed = false; - unsigned Count = SUnits.size() - 1; - for (MachineBasicBlock::iterator I = End, E = Begin; + unsigned Count = InsertPosIndex - 1; + for (MachineBasicBlock::iterator I = InsertPos, E = Begin; I != E; --Count) { MachineInstr *MI = --I; @@ -739,10 +752,16 @@ bool SchedulePostRATDList::BreakAntiDependencies() { Classes[NewReg] = Classes[AntiDepReg]; DefIndices[NewReg] = DefIndices[AntiDepReg]; KillIndices[NewReg] = KillIndices[AntiDepReg]; + assert(((KillIndices[NewReg] == ~0u) != + (DefIndices[NewReg] == ~0u)) && + "Kill and Def maps aren't consistent for NewReg!"); Classes[AntiDepReg] = 0; DefIndices[AntiDepReg] = KillIndices[AntiDepReg]; KillIndices[AntiDepReg] = ~0u; + assert(((KillIndices[AntiDepReg] == ~0u) != + (DefIndices[AntiDepReg] == ~0u)) && + "Kill and Def maps aren't consistent for AntiDepReg!"); RegRefs.erase(AntiDepReg); Changed = true; @@ -754,7 +773,6 @@ bool SchedulePostRATDList::BreakAntiDependencies() { ScanInstruction(MI, Count); } - assert(Count == ~0u && "Count mismatch!"); return Changed; } diff --git a/lib/CodeGen/ScheduleDAG.cpp b/lib/CodeGen/ScheduleDAG.cpp index db7d92218b3..a8452dff272 100644 --- a/lib/CodeGen/ScheduleDAG.cpp +++ b/lib/CodeGen/ScheduleDAG.cpp @@ -23,7 +23,7 @@ using namespace llvm; ScheduleDAG::ScheduleDAG(MachineFunction &mf) - : DAG(0), BB(0), TM(mf.getTarget()), + : TM(mf.getTarget()), TII(TM.getInstrInfo()), TRI(TM.getRegisterInfo()), TLI(TM.getTargetLowering()), @@ -47,23 +47,18 @@ void ScheduleDAG::dumpSchedule() const { /// Run - perform scheduling. /// -void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb, - MachineBasicBlock::iterator begin, - MachineBasicBlock::iterator end) { - assert((!dag || begin == end) && - "An instruction range was given for SelectionDAG scheduling!"); +void ScheduleDAG::Run(MachineBasicBlock *bb, + MachineBasicBlock::iterator insertPos) { + BB = bb; + InsertPos = insertPos; SUnits.clear(); Sequence.clear(); - DAG = dag; - BB = bb; - Begin = begin; - End = end; EntrySU = SUnit(); ExitSU = SUnit(); Schedule(); - + DOUT << "*** Final schedule ***\n"; DEBUG(dumpSchedule()); DOUT << "\n"; diff --git a/lib/CodeGen/ScheduleDAGEmit.cpp b/lib/CodeGen/ScheduleDAGEmit.cpp index 0c8435da6cb..770f5bbbdbb 100644 --- a/lib/CodeGen/ScheduleDAGEmit.cpp +++ b/lib/CodeGen/ScheduleDAGEmit.cpp @@ -33,7 +33,7 @@ void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) { } void ScheduleDAG::EmitNoop() { - TII->insertNoop(*BB, End); + TII->insertNoop(*BB, InsertPos); } void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, @@ -54,7 +54,7 @@ void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, break; } } - TII->copyRegToReg(*BB, End, Reg, VRI->second, + TII->copyRegToReg(*BB, InsertPos, Reg, VRI->second, SU->CopyDstRC, SU->CopySrcRC); } else { // Copy from physical register. @@ -63,7 +63,7 @@ void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second; isNew = isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); - TII->copyRegToReg(*BB, End, VRBase, I->getReg(), + TII->copyRegToReg(*BB, InsertPos, VRBase, I->getReg(), SU->CopyDstRC, SU->CopySrcRC); } break; diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index dac29f1161d..8e18b3d17fd 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -32,6 +32,19 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, const MachineDominatorTree &mdt) : ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {} +/// Run - perform scheduling. +/// +void ScheduleDAGInstrs::Run(MachineBasicBlock *bb, + MachineBasicBlock::iterator begin, + MachineBasicBlock::iterator end, + unsigned endcount) { + BB = bb; + Begin = begin; + InsertPosIndex = endcount; + + ScheduleDAG::Run(bb, end); +} + /// getOpcode - If this is an Instruction or a ConstantExpr, return the /// opcode value. Otherwise return UserOp1. static unsigned getOpcode(const Value *V) { @@ -146,7 +159,7 @@ void ScheduleDAGInstrs::BuildSchedGraph() { TM.getSubtarget().getSpecialAddressLatency(); // Walk the list of instructions, from bottom moving up. - for (MachineBasicBlock::iterator MII = End, MIE = Begin; + for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; MII != MIE; --MII) { MachineInstr *MI = prior(MII); const TargetInstrDesc &TID = MI->getDesc(); @@ -428,7 +441,7 @@ std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() { // For MachineInstr-based scheduling, we're rescheduling the instructions in // the block, so start by removing them from the block. - while (Begin != End) { + while (Begin != InsertPos) { MachineBasicBlock::iterator I = Begin; ++Begin; BB->remove(I); @@ -443,7 +456,7 @@ MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() { continue; } - BB->insert(End, SU->getInstr()); + BB->insert(InsertPos, SU->getInstr()); } // Update the Begin iterator, as the first instruction in the block diff --git a/lib/CodeGen/ScheduleDAGInstrs.h b/lib/CodeGen/ScheduleDAGInstrs.h index 713534ba767..00d6268d1a1 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.h +++ b/lib/CodeGen/ScheduleDAGInstrs.h @@ -120,6 +120,12 @@ namespace llvm { SmallSet LoopLiveInRegs; public: + MachineBasicBlock *BB; // Current basic block + MachineBasicBlock::iterator Begin; // The beginning of the range to + // be scheduled. The range extends + // to InsertPos. + unsigned InsertPosIndex; // The index in BB of InsertPos. + explicit ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo &mli, const MachineDominatorTree &mdt); @@ -139,6 +145,13 @@ namespace llvm { return &SUnits.back(); } + /// Run - perform scheduling. + /// + void Run(MachineBasicBlock *bb, + MachineBasicBlock::iterator begin, + MachineBasicBlock::iterator end, + unsigned endindex); + /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are /// input. virtual void BuildSchedGraph(); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index 1cd893e587d..0c343f98806 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -629,6 +629,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() { // Public Constructor Functions //===----------------------------------------------------------------------===// -llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) { +llvm::ScheduleDAGSDNodes * +llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) { return new ScheduleDAGFast(*IS->MF); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index c78ecb8aa4d..e63484e987d 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -260,8 +260,8 @@ void ScheduleDAGList::ListScheduleTopDown() { /// createTDListDAGScheduler - This creates a top-down list scheduler with a /// new hazard recognizer. This scheduler takes ownership of the hazard /// recognizer and deletes it when done. -ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS, - bool Fast) { +ScheduleDAGSDNodes * +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) { return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue(), IS->CreateTargetHazardRecognizer()); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 94006b5d8c8..07274b28998 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1358,8 +1358,8 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { // Public Constructor Functions //===----------------------------------------------------------------------===// -llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, - bool) { +llvm::ScheduleDAGSDNodes * +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); @@ -1372,8 +1372,8 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, return SD; } -llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, - bool) { +llvm::ScheduleDAGSDNodes * +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 2620c728165..ea9f47bf318 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -26,6 +26,14 @@ ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) : ScheduleDAG(mf) { } +/// Run - perform scheduling. +/// +void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb, + MachineBasicBlock::iterator insertPos) { + DAG = dag; + ScheduleDAG::Run(bb, insertPos); +} + SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { SUnit *SU = NewSUnit(Old->getNode()); SU->OrigNode = Old->OrigNode; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h index f340d38658e..af3adaafa5c 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h @@ -35,10 +35,17 @@ namespace llvm { /// class ScheduleDAGSDNodes : public ScheduleDAG { public: + SelectionDAG *DAG; // DAG of the current basic block + explicit ScheduleDAGSDNodes(MachineFunction &mf); virtual ~ScheduleDAGSDNodes() {} + /// Run - perform scheduling. + /// + void Run(SelectionDAG *dag, MachineBasicBlock *bb, + MachineBasicBlock::iterator insertPos); + /// isPassiveNode - Return true if the node is a non-scheduled leaf. /// static bool isPassiveNode(SDNode *Node) { diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp index 1d369c1bc44..852c43089da 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp @@ -125,7 +125,8 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo, } else { // Create the reg, emit the copy. VRBase = MRI.createVirtualRegister(DstRC); - bool Emitted = TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC); + bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg, + DstRC, SrcRC); if (!Emitted) { cerr << "Unable to issue a copy instruction!\n"; abort(); @@ -381,7 +382,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node, MI->addOperand(MachineOperand::CreateReg(VRBase, true)); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); MI->addOperand(MachineOperand::CreateImm(SubIdx)); - BB->insert(End, MI); + BB->insert(InsertPos, MI); } else if (Opc == TargetInstrInfo::INSERT_SUBREG || Opc == TargetInstrInfo::SUBREG_TO_REG) { SDValue N0 = Node->getOperand(0); @@ -414,7 +415,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node, // Add the subregster being inserted AddOperand(MI, N1, 0, 0, VRBaseMap); MI->addOperand(MachineOperand::CreateImm(SubIdx)); - BB->insert(End, MI); + BB->insert(InsertPos, MI); } else assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg"); @@ -478,9 +479,9 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, // Insert this instruction into the basic block using a target // specific inserter which may returns a new basic block. BB = TLI->EmitInstrWithCustomInserter(MI, BB); - Begin = End = BB->end(); + InsertPos = BB->end(); } else { - BB->insert(End, MI); + BB->insert(InsertPos, MI); } // Additional results must be an physical register def. @@ -530,7 +531,8 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, else DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, Node->getOperand(1).getValueType()); - bool Emitted = TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC); + bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg, + DstTRC, SrcTRC); if (!Emitted) { cerr << "Unable to issue a copy instruction!\n"; abort(); @@ -590,7 +592,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, break; } } - BB->insert(End, MI); + BB->insert(InsertPos, MI); break; } } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index f8d79ce3872..ed6e4fbe8c0 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -137,8 +137,8 @@ namespace llvm { //===--------------------------------------------------------------------===// /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. - ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, - bool Fast) { + ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, + bool Fast) { const TargetLowering &TLI = IS->getTargetLowering(); if (Fast) @@ -662,12 +662,12 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); // Schedule machine code. - ScheduleDAG *Scheduler = CreateScheduler(); + ScheduleDAGSDNodes *Scheduler = CreateScheduler(); if (TimePassesIsEnabled) { NamedRegionTimer T("Instruction Scheduling", GroupName); - Scheduler->Run(CurDAG, BB, BB->end(), BB->end()); + Scheduler->Run(CurDAG, BB, BB->end()); } else { - Scheduler->Run(CurDAG, BB, BB->end(), BB->end()); + Scheduler->Run(CurDAG, BB, BB->end()); } if (ViewSUnitDAGs) Scheduler->viewGraph(); @@ -1068,7 +1068,7 @@ SelectionDAGISel::FinishBasicBlock() { /// via the SchedulerRegistry, use it, otherwise select the /// one preferred by the target. /// -ScheduleDAG *SelectionDAGISel::CreateScheduler() { +ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); if (!Ctor) {