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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
formatting change, reduce indentation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66642 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
600fec3cea
commit
47b4ce8529
@ -8098,74 +8098,72 @@ static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
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/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
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static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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DebugLoc dl = N->getDebugLoc();
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const X86Subtarget *Subtarget) {
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DebugLoc DL = N->getDebugLoc();
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SDValue Cond = N->getOperand(0);
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// Get the LHS/RHS of the select.
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SDValue LHS = N->getOperand(1);
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SDValue RHS = N->getOperand(2);
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// If we have SSE[12] support, try to form min/max nodes.
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if (Subtarget->hasSSE2() &&
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(N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
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if (Cond.getOpcode() == ISD::SETCC) {
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// Get the LHS/RHS of the select.
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SDValue LHS = N->getOperand(1);
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SDValue RHS = N->getOperand(2);
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
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Cond.getOpcode() == ISD::SETCC) {
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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unsigned Opcode = 0;
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if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
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switch (CC) {
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default: break;
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case ISD::SETOLE: // (X <= Y) ? X : Y -> min
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case ISD::SETULE:
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case ISD::SETLE:
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if (!UnsafeFPMath) break;
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// FALL THROUGH.
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case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
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case ISD::SETLT:
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Opcode = X86ISD::FMIN;
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break;
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unsigned Opcode = 0;
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if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
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switch (CC) {
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default: break;
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case ISD::SETOLE: // (X <= Y) ? X : Y -> min
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case ISD::SETULE:
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case ISD::SETLE:
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if (!UnsafeFPMath) break;
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// FALL THROUGH.
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case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
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case ISD::SETLT:
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Opcode = X86ISD::FMIN;
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break;
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case ISD::SETOGT: // (X > Y) ? X : Y -> max
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case ISD::SETUGT:
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case ISD::SETGT:
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if (!UnsafeFPMath) break;
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// FALL THROUGH.
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case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
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case ISD::SETGE:
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Opcode = X86ISD::FMAX;
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break;
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}
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} else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
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switch (CC) {
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default: break;
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case ISD::SETOGT: // (X > Y) ? Y : X -> min
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case ISD::SETUGT:
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case ISD::SETGT:
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if (!UnsafeFPMath) break;
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// FALL THROUGH.
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case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
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case ISD::SETGE:
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Opcode = X86ISD::FMIN;
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break;
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case ISD::SETOLE: // (X <= Y) ? Y : X -> max
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case ISD::SETULE:
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case ISD::SETLE:
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if (!UnsafeFPMath) break;
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// FALL THROUGH.
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case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
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case ISD::SETLT:
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Opcode = X86ISD::FMAX;
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break;
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}
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case ISD::SETOGT: // (X > Y) ? X : Y -> max
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case ISD::SETUGT:
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case ISD::SETGT:
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if (!UnsafeFPMath) break;
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// FALL THROUGH.
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case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
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case ISD::SETGE:
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Opcode = X86ISD::FMAX;
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break;
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}
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} else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
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switch (CC) {
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default: break;
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case ISD::SETOGT: // (X > Y) ? Y : X -> min
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case ISD::SETUGT:
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case ISD::SETGT:
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if (!UnsafeFPMath) break;
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// FALL THROUGH.
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case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
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case ISD::SETGE:
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Opcode = X86ISD::FMIN;
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break;
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if (Opcode)
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return DAG.getNode(Opcode, dl, N->getValueType(0), LHS, RHS);
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case ISD::SETOLE: // (X <= Y) ? Y : X -> max
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case ISD::SETULE:
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case ISD::SETLE:
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if (!UnsafeFPMath) break;
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// FALL THROUGH.
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case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
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case ISD::SETLT:
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Opcode = X86ISD::FMAX;
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break;
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}
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}
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if (Opcode)
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return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
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}
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return SDValue();
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}
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@ -8186,7 +8184,7 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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SDValue ShAmtOp = N->getOperand(1);
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MVT EltVT = VT.getVectorElementType();
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DebugLoc dl = N->getDebugLoc();
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DebugLoc DL = N->getDebugLoc();
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SDValue BaseShAmt;
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if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
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unsigned NumElts = VT.getVectorNumElements();
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@ -8206,15 +8204,15 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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}
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} else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
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isSplatMask(ShAmtOp.getOperand(2).getNode())) {
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BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ShAmtOp,
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BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
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DAG.getIntPtrConstant(0));
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} else
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return SDValue();
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if (EltVT.bitsGT(MVT::i32))
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BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
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BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
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else if (EltVT.bitsLT(MVT::i32))
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BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BaseShAmt);
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BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
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// The shift amount is identical so we can do a vector shift.
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SDValue ValOp = N->getOperand(0);
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@ -8224,39 +8222,39 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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break;
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case ISD::SHL:
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if (VT == MVT::v2i64)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v4i32)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v8i16)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
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ValOp, BaseShAmt);
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break;
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case ISD::SRA:
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if (VT == MVT::v4i32)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v8i16)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
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ValOp, BaseShAmt);
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break;
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case ISD::SRL:
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if (VT == MVT::v2i64)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v4i32)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v8i16)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
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ValOp, BaseShAmt);
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break;
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@ -8298,33 +8296,33 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
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}
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}
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if (Ld) {
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DebugLoc dl = N->getDebugLoc();
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DebugLoc DL = N->getDebugLoc();
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// If we are a 64-bit capable x86, lower to a single movq load/store pair.
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if (Subtarget->is64Bit()) {
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SDValue NewLd = DAG.getLoad(MVT::i64, dl, Ld->getChain(),
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SDValue NewLd = DAG.getLoad(MVT::i64, DL, Ld->getChain(),
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Ld->getBasePtr(), Ld->getSrcValue(),
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Ld->getSrcValueOffset(), Ld->isVolatile(),
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Ld->getAlignment());
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SDValue NewChain = NewLd.getValue(1);
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if (TokenFactorIndex != -1) {
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Ops.push_back(NewChain);
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NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
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NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Ops[0],
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Ops.size());
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}
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return DAG.getStore(NewChain, dl, NewLd, St->getBasePtr(),
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return DAG.getStore(NewChain, DL, NewLd, St->getBasePtr(),
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St->getSrcValue(), St->getSrcValueOffset(),
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St->isVolatile(), St->getAlignment());
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}
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// Otherwise, lower to two 32-bit copies.
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SDValue LoAddr = Ld->getBasePtr();
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SDValue HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr,
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SDValue HiAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, LoAddr,
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DAG.getConstant(4, MVT::i32));
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SDValue LoLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), LoAddr,
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SDValue LoLd = DAG.getLoad(MVT::i32, DL, Ld->getChain(), LoAddr,
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Ld->getSrcValue(), Ld->getSrcValueOffset(),
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Ld->isVolatile(), Ld->getAlignment());
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SDValue HiLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), HiAddr,
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SDValue HiLd = DAG.getLoad(MVT::i32, DL, Ld->getChain(), HiAddr,
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Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
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Ld->isVolatile(),
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MinAlign(Ld->getAlignment(), 4));
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@ -8333,23 +8331,23 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
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if (TokenFactorIndex != -1) {
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Ops.push_back(LoLd);
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Ops.push_back(HiLd);
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NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
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NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Ops[0],
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Ops.size());
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}
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LoAddr = St->getBasePtr();
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HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr,
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HiAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, LoAddr,
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DAG.getConstant(4, MVT::i32));
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SDValue LoSt = DAG.getStore(NewChain, dl, LoLd, LoAddr,
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SDValue LoSt = DAG.getStore(NewChain, DL, LoLd, LoAddr,
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St->getSrcValue(), St->getSrcValueOffset(),
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St->isVolatile(), St->getAlignment());
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SDValue HiSt = DAG.getStore(NewChain, dl, HiLd, HiAddr,
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SDValue HiSt = DAG.getStore(NewChain, DL, HiLd, HiAddr,
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St->getSrcValue(),
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St->getSrcValueOffset() + 4,
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St->isVolatile(),
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MinAlign(St->getAlignment(), 4));
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoSt, HiSt);
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return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, LoSt, HiSt);
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}
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}
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return SDValue();
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