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ARM: Add subtarget feature for CRC

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Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Differential Revision: http://llvm-reviews.chandlerc.com/D2036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bernard Ogden 2013-10-29 09:47:35 +00:00
parent 72202297a9
commit 47c6d17b1c
7 changed files with 40 additions and 18 deletions
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6
lib/Target/ARM/ARM.td
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@ -70,6 +70,8 @@ def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
"Enable support for Cryptography extensions", "Enable support for Cryptography extensions",
[FeatureNEON]>; [FeatureNEON]>;
def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
"Enable support for CRC instructions">;
// Some processors have FP multiply-accumulate instructions that don't // Some processors have FP multiply-accumulate instructions that don't
// play nicely with other VFP / NEON instructions, and it's generally better // play nicely with other VFP / NEON instructions, and it's generally better
@ -202,13 +204,13 @@ def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
"Cortex-A53 ARM processors", "Cortex-A53 ARM processors",
[FeatureMP, FeatureHWDiv, FeatureHWDivARM, [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
FeatureTrustZone, FeatureT2XtPk, FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto]>; FeatureCrypto, FeatureCRC]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", "Cortex-A57 ARM processors",
[FeatureMP, FeatureHWDiv, FeatureHWDivARM, [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
FeatureTrustZone, FeatureT2XtPk, FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto]>; FeatureCrypto, FeatureCRC]>;
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
"Cortex-R5 ARM processors", "Cortex-R5 ARM processors",

4
lib/Target/ARM/ARMInstrInfo.td
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@ -221,6 +221,8 @@ def HasNEON : Predicate<"Subtarget->hasNEON()">,
AssemblerPredicate<"FeatureNEON", "NEON">; AssemblerPredicate<"FeatureNEON", "NEON">;
def HasCrypto : Predicate<"Subtarget->hasCrypto()">, def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
AssemblerPredicate<"FeatureCrypto", "crypto">; AssemblerPredicate<"FeatureCrypto", "crypto">;
def HasCRC : Predicate<"Subtarget->hasCRC()">,
AssemblerPredicate<"FeatureCRC", "crc">;
def HasFP16 : Predicate<"Subtarget->hasFP16()">, def HasFP16 : Predicate<"Subtarget->hasFP16()">,
AssemblerPredicate<"FeatureFP16","half-float">; AssemblerPredicate<"FeatureFP16","half-float">;
def HasDivide : Predicate<"Subtarget->hasDivide()">, def HasDivide : Predicate<"Subtarget->hasDivide()">,
@ -4032,7 +4034,7 @@ class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
: AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
!strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
[(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
Requires<[IsARM, HasV8]> { Requires<[IsARM, HasV8, HasCRC]> {
bits<4> Rd; bits<4> Rd;
bits<4> Rn; bits<4> Rn;
bits<4> Rm; bits<4> Rm;

2
lib/Target/ARM/ARMInstrThumb2.td
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@ -3027,7 +3027,7 @@ class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
: T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
!strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"), !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
[(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>, [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
Requires<[IsThumb2, HasV8]> { Requires<[IsThumb2, HasV8, HasCRC]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b010110; let Inst{26-21} = 0b010110;
let Inst{20} = C; let Inst{20} = C;

4
lib/Target/ARM/ARMSubtarget.h
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@ -165,6 +165,9 @@ protected:
/// HasCrypto - if true, processor supports Cryptography extensions /// HasCrypto - if true, processor supports Cryptography extensions
bool HasCrypto; bool HasCrypto;
/// HasCRC - if true, processor supports CRC instructions
bool HasCRC;
/// AllowsUnalignedMem - If true, the subtarget allows unaligned memory /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
/// accesses for some types. For details, see /// accesses for some types. For details, see
/// ARMTargetLowering::allowsUnalignedMemoryAccesses(). /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
@ -256,6 +259,7 @@ public:
bool hasFPARMv8() const { return HasFPARMv8; } bool hasFPARMv8() const { return HasFPARMv8; }
bool hasNEON() const { return HasNEON; } bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; } bool hasCrypto() const { return HasCrypto; }
bool hasCRC() const { return HasCRC; }
bool useNEONForSinglePrecisionFP() const { bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; } return hasNEON() && UseNEONForSinglePrecisionFP; }

4
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
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@ -105,8 +105,8 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
if (SubVer == '8') { if (SubVer == '8') {
if (NoCPU) if (NoCPU)
// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, FeatureMP, // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, FeatureMP,
// FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto // FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto, FeatureCRC
ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto"; ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto,+crc";
else else
// Use CPU to figure out the exact features // Use CPU to figure out the exact features
ARMArchFeature = "+v8"; ARMArchFeature = "+v8";

19
test/MC/ARM/crc32-thumb.s
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@ -1,5 +1,6 @@
@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 @ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
crc32b r0, r1, r2 crc32b r0, r1, r2
crc32h r0, r1, r2 crc32h r0, r1, r2
crc32w r0, r1, r2 crc32w r0, r1, r2
@ -7,9 +8,12 @@
@ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0] @ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0] @ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0] @ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
crc32cb r0, r1, r2 crc32cb r0, r1, r2
crc32ch r0, r1, r2 crc32ch r0, r1, r2
@ -18,6 +22,9 @@
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0] @ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0] @ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0] @ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc

19
test/MC/ARM/crc32.s
View File

@ -1,5 +1,6 @@
@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
crc32b r0, r1, r2 crc32b r0, r1, r2
crc32h r0, r1, r2 crc32h r0, r1, r2
crc32w r0, r1, r2 crc32w r0, r1, r2
@ -7,9 +8,12 @@
@ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1] @ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1] @ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1] @ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1]
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
crc32cb r0, r1, r2 crc32cb r0, r1, r2
crc32ch r0, r1, r2 crc32ch r0, r1, r2
@ -18,6 +22,9 @@
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1] @ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1] @ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1] @ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1]
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc