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[Hexagon] Adding encoding information for absolute-reg mode stores. Xfailing a test until constant extenders are correctly put in the same packet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228158 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
282314741d
commit
47d6e4d009
@ -1533,14 +1533,14 @@ int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
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switch (MI->getOpcode()) {
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default: llvm_unreachable("Unknown .new type");
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// store new value byte
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case Hexagon::STrib_shl_V4:
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return Hexagon::STrib_shl_nv_V4;
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case Hexagon::S4_storerb_ur:
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return Hexagon::S4_storerbnew_ur;
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case Hexagon::STrih_shl_V4:
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return Hexagon::STrih_shl_nv_V4;
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case Hexagon::S4_storerh_ur:
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return Hexagon::S4_storerhnew_ur;
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case Hexagon::STriw_shl_V4:
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return Hexagon::STriw_shl_nv_V4;
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case Hexagon::S4_storeri_ur:
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return Hexagon::S4_storerinew_ur;
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}
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return 0;
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@ -743,6 +743,128 @@ let isNVStorable = 0 in {
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0b110, DoubleWordAccess>;
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}
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let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
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isExtended = 1, opExtentBits= 6 in
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class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
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MemAccessSize AccessSz >
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: NVInst <(outs IntRegs:$dst),
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(ins u6Ext:$addr, IntRegs:$src),
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mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
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bits<5> dst;
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bits<6> addr;
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bits<3> src;
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let accessSize = AccessSz;
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let BaseOpcode = BaseOp#"_AbsSet";
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let IClass = 0b1010;
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let Inst{27-21} = 0b1011101;
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let Inst{20-16} = dst;
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let Inst{13-11} = 0b000;
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let Inst{12-11} = MajOp;
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let Inst{10-8} = src;
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let Inst{7} = 0b1;
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let Inst{5-0} = addr;
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}
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let mayStore = 1, addrMode = AbsoluteSet in {
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def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
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def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
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def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
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}
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let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
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addrMode = BaseLongOffset, AddedComplexity = 40 in
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class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
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bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
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: STInst<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
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mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
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[]>, ImmRegShl, NewValueRel {
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bits<5> src1;
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bits<2> src2;
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bits<6> src3;
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bits<5> src4;
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let accessSize = AccessSz;
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let CextOpcode = CextOp;
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let BaseOpcode = CextOp#"_shl";
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let IClass = 0b1010;
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let Inst{27-24} =0b1101;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = src1;
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let Inst{13} = src2{1};
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let Inst{12-8} = src4;
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let Inst{7} = 0b1;
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let Inst{6} = src2{0};
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let Inst{5-0} = src3;
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}
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def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
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def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
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HalfWordAccess>;
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def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
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HalfWordAccess, 1>;
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def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
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def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
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DoubleWordAccess>;
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let AddedComplexity = 40 in
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multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
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PatFrag stOp> {
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def : Pat<(stOp (VT RC:$src4),
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(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
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u0AlwaysExtPred:$src3)),
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(MI IntRegs:$src1, u2ImmPred:$src2, u0AlwaysExtPred:$src3, RC:$src4)>;
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def : Pat<(stOp (VT RC:$src4),
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(add (shl IntRegs:$src1, u2ImmPred:$src2),
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(HexagonCONST32 tglobaladdr:$src3))),
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(MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
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def : Pat<(stOp (VT RC:$src4),
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(add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
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(MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
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}
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defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
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defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
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defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
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defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
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let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
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opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
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class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
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MemAccessSize AccessSz>
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: NVInst <(outs ),
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(ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
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mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
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bits<5> src1;
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bits<2> src2;
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bits<6> src3;
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bits<3> src4;
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let CextOpcode = CextOp;
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let BaseOpcode = CextOp#"_shl";
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let IClass = 0b1010;
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let Inst{27-21} = 0b1101101;
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let Inst{12-11} = 0b00;
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let Inst{7} = 0b1;
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let Inst{20-16} = src1;
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let Inst{13} = src2{1};
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let Inst{12-11} = MajOp;
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let Inst{10-8} = src4;
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let Inst{6} = src2{0};
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let Inst{5-0} = src3;
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}
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def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
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def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
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def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
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//===----------------------------------------------------------------------===//
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// Template classes for the non-predicated store instructions with
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// base + register offset addressing mode
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@ -905,8 +1027,7 @@ multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
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}
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}
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let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
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isCodeGenOnly = 0 in {
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let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
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let accessSize = ByteAccess in
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defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
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ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
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@ -926,83 +1047,18 @@ let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
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defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
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}
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let Predicates = [HasV4T], AddedComplexity = 10 in {
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def : Pat<(truncstorei8 (i32 IntRegs:$src4),
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(add IntRegs:$src1, (shl IntRegs:$src2,
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u2ImmPred:$src3))),
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(S4_storerb_rr IntRegs:$src1, IntRegs:$src2,
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u2ImmPred:$src3, IntRegs:$src4)>;
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class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
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: Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
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(i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
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(MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
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def : Pat<(truncstorei16 (i32 IntRegs:$src4),
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(add IntRegs:$src1, (shl IntRegs:$src2,
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u2ImmPred:$src3))),
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(S4_storerh_rr IntRegs:$src1, IntRegs:$src2,
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u2ImmPred:$src3, IntRegs:$src4)>;
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def : Pat<(store (i32 IntRegs:$src4),
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(add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
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(S4_storeri_rr IntRegs:$src1, IntRegs:$src2,
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u2ImmPred:$src3, IntRegs:$src4)>;
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def : Pat<(store (i64 DoubleRegs:$src4),
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(add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
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(S4_storerd_rr IntRegs:$src1, IntRegs:$src2,
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u2ImmPred:$src3, DoubleRegs:$src4)>;
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let AddedComplexity = 40 in {
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def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
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def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
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def: Storexs_pat<store, I32, S4_storeri_rr>;
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def: Storexs_pat<store, I64, S4_storerd_rr>;
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}
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let isExtended = 1, opExtendable = 2 in
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class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
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STInst<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
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mnemonic#"($src1<<#$src2+##$src3) = $src4",
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[(stOp (VT RC:$src4),
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(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
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u0AlwaysExtPred:$src3))]>,
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Requires<[HasV4T]>;
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let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
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class T_ST_LongOff_nv <string mnemonic> :
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NVInst_V4<(outs),
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(ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
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mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
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let BaseOpcode = BaseOp#"_shl" in {
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let isNVStorable = 1 in
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def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
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def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
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}
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}
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let AddedComplexity = 10, validSubTargets = HasV4SubT in {
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def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
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defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
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defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
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defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
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}
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let AddedComplexity = 40 in
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multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
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PatFrag stOp> {
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def : Pat<(stOp (VT RC:$src4),
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(add (shl IntRegs:$src1, u2ImmPred:$src2),
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(NumUsesBelowThresCONST32 tglobaladdr:$src3))),
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(I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
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def : Pat<(stOp (VT RC:$src4),
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(add IntRegs:$src1,
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(NumUsesBelowThresCONST32 tglobaladdr:$src3))),
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(I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
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}
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defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
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defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
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defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
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defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
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// memd(Rx++#s4:3)=Rtt
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// memd(Rx++#s4:3:circ(Mu))=Rtt
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// memd(Rx++I:circ(Mu))=Rtt
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@ -1,3 +1,4 @@
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; XFAIL:
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we don't generate an invalid packet with too many instructions
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@ -7,7 +8,7 @@
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; CHECK: {
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; CHECK-NOT: call abort
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; CHECK: memw(##0)
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; CHECK: memw(r{{[0-9+]}}<<#2+##4)
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; CHECK: memw(r{{[0-9+]}}<<#2 + ##4)
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; CHECK: }
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%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { i8*, void (%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*)*, i32, i32, i8*, [23 x i32]* }
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