Change the Spiller interface to take a LiveRangeEdit reference.

This makes it possible to register delegates and get callbacks when the spiller
edits live ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127389 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-03-10 01:51:42 +00:00
parent 38f6bd0fc8
commit 47dbf6cef7
7 changed files with 34 additions and 50 deletions

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@ -24,15 +24,11 @@
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
static cl::opt<bool>
VerifySpills("verify-spills", cl::desc("Verify after each spill/split"));
namespace { namespace {
class InlineSpiller : public Spiller { class InlineSpiller : public Spiller {
MachineFunctionPass &pass_; MachineFunctionPass &pass_;
@ -73,10 +69,6 @@ public:
tri_(*mf.getTarget().getRegisterInfo()), tri_(*mf.getTarget().getRegisterInfo()),
reserved_(tri_.getReservedRegs(mf_)) {} reserved_(tri_.getReservedRegs(mf_)) {}
void spill(LiveInterval *li,
SmallVectorImpl<LiveInterval*> &newIntervals,
const SmallVectorImpl<LiveInterval*> *spillIs);
void spill(LiveRangeEdit &); void spill(LiveRangeEdit &);
private: private:
@ -96,8 +88,6 @@ namespace llvm {
Spiller *createInlineSpiller(MachineFunctionPass &pass, Spiller *createInlineSpiller(MachineFunctionPass &pass,
MachineFunction &mf, MachineFunction &mf,
VirtRegMap &vrm) { VirtRegMap &vrm) {
if (VerifySpills)
mf.verify(&pass, "When creating inline spiller");
return new InlineSpiller(pass, mf, vrm); return new InlineSpiller(pass, mf, vrm);
} }
} }
@ -330,15 +320,6 @@ void InlineSpiller::insertSpill(LiveInterval &NewLI,
NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI)); NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
} }
void InlineSpiller::spill(LiveInterval *li,
SmallVectorImpl<LiveInterval*> &newIntervals,
const SmallVectorImpl<LiveInterval*> *spillIs) {
LiveRangeEdit edit(*li, newIntervals, 0, spillIs);
spill(edit);
if (VerifySpills)
mf_.verify(&pass_, "After inline spill");
}
void InlineSpiller::spill(LiveRangeEdit &edit) { void InlineSpiller::spill(LiveRangeEdit &edit) {
edit_ = &edit; edit_ = &edit;
assert(!TargetRegisterInfo::isStackSlot(edit.getReg()) assert(!TargetRegisterInfo::isStackSlot(edit.getReg())

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@ -76,7 +76,7 @@ public:
/// rematerializing values because they are about to be removed. /// rematerializing values because they are about to be removed.
LiveRangeEdit(LiveInterval &parent, LiveRangeEdit(LiveInterval &parent,
SmallVectorImpl<LiveInterval*> &newRegs, SmallVectorImpl<LiveInterval*> &newRegs,
Delegate *delegate, Delegate *delegate = 0,
const SmallVectorImpl<LiveInterval*> *uselessRegs = 0) const SmallVectorImpl<LiveInterval*> *uselessRegs = 0)
: parent_(parent), newRegs_(newRegs), : parent_(parent), newRegs_(newRegs),
delegate_(delegate), delegate_(delegate),
@ -95,6 +95,13 @@ public:
bool empty() const { return size() == 0; } bool empty() const { return size() == 0; }
LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; } LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; }
/// FIXME: Temporary accessors until we can get rid of
/// LiveIntervals::AddIntervalsForSpills
SmallVectorImpl<LiveInterval*> *getNewVRegs() { return &newRegs_; }
const SmallVectorImpl<LiveInterval*> *getUselessVRegs() {
return uselessRegs_;
}
/// create - Create a new register with the same class and stack slot as /// create - Create a new register with the same class and stack slot as
/// parent. /// parent.
LiveInterval &create(MachineRegisterInfo&, LiveIntervals&, VirtRegMap&); LiveInterval &create(MachineRegisterInfo&, LiveIntervals&, VirtRegMap&);

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@ -14,6 +14,7 @@
#define DEBUG_TYPE "regalloc" #define DEBUG_TYPE "regalloc"
#include "LiveIntervalUnion.h" #include "LiveIntervalUnion.h"
#include "LiveRangeEdit.h"
#include "RegAllocBase.h" #include "RegAllocBase.h"
#include "RenderMachineFunction.h" #include "RenderMachineFunction.h"
#include "Spiller.h" #include "Spiller.h"
@ -344,7 +345,8 @@ void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
unassign(SpilledVReg, PhysReg); unassign(SpilledVReg, PhysReg);
// Spill the extracted interval. // Spill the extracted interval.
spiller().spill(&SpilledVReg, SplitVRegs, &PendingSpills); LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
spiller().spill(LRE);
} }
// After extracting segments, the query's results are invalid. But keep the // After extracting segments, the query's results are invalid. But keep the
// contents valid until we're done accessing pendingSpills. // contents valid until we're done accessing pendingSpills.
@ -469,7 +471,8 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
} }
// No other spill candidates were found, so spill the current VirtReg. // No other spill candidates were found, so spill the current VirtReg.
DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
spiller().spill(&VirtReg, SplitVRegs, 0); LiveRangeEdit LRE(VirtReg, SplitVRegs);
spiller().spill(LRE);
// The live virtual register requesting allocation was spilled, so tell // The live virtual register requesting allocation was spilled, so tell
// the caller not to allocate anything during this round. // the caller not to allocate anything during this round.

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@ -1253,7 +1253,8 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
// Finally spill VirtReg itself. // Finally spill VirtReg itself.
NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled); NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
spiller().spill(&VirtReg, NewVRegs, 0); LiveRangeEdit LRE(VirtReg, NewVRegs, this);
spiller().spill(LRE);
// The live virtual register requesting allocation was spilled, so tell // The live virtual register requesting allocation was spilled, so tell
// the caller not to allocate anything during this round. // the caller not to allocate anything during this round.

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@ -13,6 +13,7 @@
#define DEBUG_TYPE "regalloc" #define DEBUG_TYPE "regalloc"
#include "LiveDebugVariables.h" #include "LiveDebugVariables.h"
#include "LiveRangeEdit.h"
#include "VirtRegMap.h" #include "VirtRegMap.h"
#include "VirtRegRewriter.h" #include "VirtRegRewriter.h"
#include "Spiller.h" #include "Spiller.h"
@ -1230,7 +1231,8 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
if (cur->weight != HUGE_VALF && cur->weight <= minWeight) { if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n'); DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
SmallVector<LiveInterval*, 8> added; SmallVector<LiveInterval*, 8> added;
spiller_->spill(cur, added, 0); LiveRangeEdit LRE(*cur, added);
spiller_->spill(LRE);
std::sort(added.begin(), added.end(), LISorter()); std::sort(added.begin(), added.end(), LISorter());
if (added.empty()) if (added.empty())
@ -1306,7 +1308,8 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n'); DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
if (sli->beginIndex() < earliestStart) if (sli->beginIndex() < earliestStart)
earliestStart = sli->beginIndex(); earliestStart = sli->beginIndex();
spiller_->spill(sli, added, &spillIs); LiveRangeEdit LRE(*sli, added, 0, &spillIs);
spiller_->spill(LRE);
spilled.insert(sli->reg); spilled.insert(sli->reg);
} }

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@ -11,6 +11,7 @@
#include "Spiller.h" #include "Spiller.h"
#include "VirtRegMap.h" #include "VirtRegMap.h"
#include "LiveRangeEdit.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
@ -180,11 +181,9 @@ public:
VirtRegMap &vrm) VirtRegMap &vrm)
: SpillerBase(pass, mf, vrm) {} : SpillerBase(pass, mf, vrm) {}
void spill(LiveInterval *li, void spill(LiveRangeEdit &LRE) {
SmallVectorImpl<LiveInterval*> &newIntervals,
const SmallVectorImpl<LiveInterval*>*) {
// Ignore spillIs - we don't use it. // Ignore spillIs - we don't use it.
trivialSpillEverywhere(li, newIntervals); trivialSpillEverywhere(&LRE.getParent(), *LRE.getNewVRegs());
} }
}; };
@ -210,22 +209,22 @@ public:
vrm(&vrm) {} vrm(&vrm) {}
/// Falls back on LiveIntervals::addIntervalsForSpills. /// Falls back on LiveIntervals::addIntervalsForSpills.
void spill(LiveInterval *li, void spill(LiveRangeEdit &LRE) {
SmallVectorImpl<LiveInterval*> &newIntervals,
const SmallVectorImpl<LiveInterval*> *spillIs) {
std::vector<LiveInterval*> added = std::vector<LiveInterval*> added =
lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm); lis->addIntervalsForSpills(LRE.getParent(), LRE.getUselessVRegs(),
newIntervals.insert(newIntervals.end(), added.begin(), added.end()); loopInfo, *vrm);
LRE.getNewVRegs()->insert(LRE.getNewVRegs()->end(),
added.begin(), added.end());
// Update LiveStacks. // Update LiveStacks.
int SS = vrm->getStackSlot(li->reg); int SS = vrm->getStackSlot(LRE.getReg());
if (SS == VirtRegMap::NO_STACK_SLOT) if (SS == VirtRegMap::NO_STACK_SLOT)
return; return;
const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(li->reg); const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg());
LiveInterval &SI = lss->getOrCreateInterval(SS, RC); LiveInterval &SI = lss->getOrCreateInterval(SS, RC);
if (!SI.hasAtLeastOneValue()) if (!SI.hasAtLeastOneValue())
SI.getNextValue(SlotIndex(), 0, lss->getVNInfoAllocator()); SI.getNextValue(SlotIndex(), 0, lss->getVNInfoAllocator());
SI.MergeRangesInAsValue(*li, SI.getValNumInfo(0)); SI.MergeRangesInAsValue(LRE.getParent(), SI.getValNumInfo(0));
} }
}; };

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@ -12,11 +12,9 @@
namespace llvm { namespace llvm {
class LiveInterval; class LiveRangeEdit;
class MachineFunction; class MachineFunction;
class MachineFunctionPass; class MachineFunctionPass;
class SlotIndex;
template <typename T> class SmallVectorImpl;
class VirtRegMap; class VirtRegMap;
/// Spiller interface. /// Spiller interface.
@ -27,16 +25,8 @@ namespace llvm {
public: public:
virtual ~Spiller() = 0; virtual ~Spiller() = 0;
/// spill - Spill the given live interval. The method used will depend on /// spill - Spill the LRE.getParent() live interval.
/// the Spiller implementation selected. virtual void spill(LiveRangeEdit &LRE) = 0;
///
/// @param li The live interval to be spilled.
/// @param spillIs A list of intervals that are about to be spilled,
/// and so cannot be used for remat etc.
/// @param newIntervals The newly created intervals will be appended here.
virtual void spill(LiveInterval *li,
SmallVectorImpl<LiveInterval*> &newIntervals,
const SmallVectorImpl<LiveInterval*> *spillIs) = 0;
}; };