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Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -126,6 +126,9 @@ private:
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/// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
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SDNode *SelectDYN_ALLOC(SDValue Op);
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/// SelectV6T2BitfielsOp - Select SBFX/UBFX instructions for ARM.
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SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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@ -138,6 +141,31 @@ private:
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};
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}
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/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
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/// operand. If so Imm will receive the 32-bit value.
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static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
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if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
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Imm = cast<ConstantSDNode>(N)->getZExtValue();
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return true;
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}
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return false;
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}
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// isInt32Immediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isInt32Immediate(SDValue N, unsigned &Imm) {
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return isInt32Immediate(N.getNode(), Imm);
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}
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// isOpcWithIntImmediate - This method tests to see if the node is a specific
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// opcode and that it has a immediate integer right operand.
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// If so Imm will receive the 32 bit value.
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static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
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return N->getOpcode() == Opc &&
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isInt32Immediate(N->getOperand(1).getNode(), Imm);
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}
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void ARMDAGToDAGISel::InstructionSelect() {
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DEBUG(BB->dump());
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@ -942,6 +970,32 @@ SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
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VT, SDValue(Pair, 0), V1, SubReg1);
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}
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SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
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unsigned Opc) {
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if (!Subtarget->hasV6T2Ops())
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return NULL;
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unsigned Shl_imm = 0;
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if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)){
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assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
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unsigned Srl_imm = 0;
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if (isInt32Immediate(Op.getOperand(1), Srl_imm)) {
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assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
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unsigned Width = 32 - Srl_imm;
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int LSB = Srl_imm - Shl_imm;
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if ((LSB + Width) > 32)
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return NULL;
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SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
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SDValue Ops[] = { Op.getOperand(0).getOperand(0),
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CurDAG->getTargetConstant(LSB, MVT::i32),
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CurDAG->getTargetConstant(Width, MVT::i32),
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getAL(CurDAG), Reg0 };
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return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32, Ops, 5);
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}
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}
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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SDNode *N = Op.getNode();
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DebugLoc dl = N->getDebugLoc();
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@ -1019,6 +1073,16 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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}
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case ARMISD::DYN_ALLOC:
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return SelectDYN_ALLOC(Op);
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case ISD::SRL:
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if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
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Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
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return I;
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break;
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case ISD::SRA:
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if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
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Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
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return I;
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break;
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case ISD::MUL:
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if (Subtarget->isThumb1Only())
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break;
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@ -284,6 +284,10 @@ def so_imm2part_2 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
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def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
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return (int32_t)N->getZExtValue() < 32;
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}]>;
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// Define ARM specific addressing modes.
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@ -1014,6 +1018,24 @@ defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
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// TODO: UXT(A){B|H}16
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def SBFX : I<(outs GPR:$dst),
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(ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
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AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
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"sbfx", " $dst, $src, $lsb, $width", "", []>,
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Requires<[IsARM, HasV6T2]> {
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let Inst{27-21} = 0b0111101;
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let Inst{6-4} = 0b101;
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}
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def UBFX : I<(outs GPR:$dst),
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(ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
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AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
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"ubfx", " $dst, $src, $lsb, $width", "", []>,
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Requires<[IsARM, HasV6T2]> {
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let Inst{27-21} = 0b0111111;
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let Inst{6-4} = 0b101;
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}
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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@ -767,6 +767,12 @@ def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
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IIC_iALUi, "bfc", " $dst, $imm",
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[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
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def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
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IIC_iALUi, "sbfx", " $dst, $src, $lsb, $width", []>;
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def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
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IIC_iALUi, "ubfx", " $dst, $src, $lsb, $width", []>;
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// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
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defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
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37
test/CodeGen/ARM/sbfx.ll
Normal file
37
test/CodeGen/ARM/sbfx.ll
Normal file
@ -0,0 +1,37 @@
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; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
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define i32 @f1(i32 %a) {
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entry:
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; CHECK: f1:
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; CHECK: sbfx r0, r0, #0, #20
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%tmp = shl i32 %a, 12
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%tmp2 = ashr i32 %tmp, 12
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ret i32 %tmp2
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}
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define i32 @f2(i32 %a) {
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entry:
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; CHECK: f2:
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; CHECK: ubfx r0, r0, #0, #20
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%tmp = shl i32 %a, 12
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%tmp2 = lshr i32 %tmp, 12
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ret i32 %tmp2
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}
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define i32 @f3(i32 %a) {
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entry:
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; CHECK: f3:
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; CHECK: sbfx r0, r0, #5, #3
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%tmp = shl i32 %a, 24
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%tmp2 = ashr i32 %tmp, 29
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ret i32 %tmp2
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}
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define i32 @f4(i32 %a) {
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entry:
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; CHECK: f4:
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; CHECK: ubfx r0, r0, #5, #3
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%tmp = shl i32 %a, 24
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%tmp2 = lshr i32 %tmp, 29
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ret i32 %tmp2
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}
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