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https://github.com/c64scene-ar/llvm-6502.git
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- Use movaps to store 128-bit vector integers.
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
e35c218f3e
commit
48090aa814
@ -265,19 +265,19 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
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// FIXME: add MMX packed arithmetics
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
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}
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if (TM.getSubtarget<X86Subtarget>().hasSSE1()) {
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addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
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setOperationAction(ISD::ADD , MVT::v4f32, Legal);
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setOperationAction(ISD::SUB , MVT::v4f32, Legal);
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setOperationAction(ISD::MUL , MVT::v4f32, Legal);
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setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
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setOperationAction(ISD::ADD, MVT::v4f32, Legal);
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setOperationAction(ISD::SUB, MVT::v4f32, Legal);
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setOperationAction(ISD::MUL, MVT::v4f32, Legal);
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setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
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}
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if (TM.getSubtarget<X86Subtarget>().hasSSE2()) {
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@ -288,15 +288,17 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
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setOperationAction(ISD::ADD , MVT::v2f64, Legal);
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setOperationAction(ISD::SUB , MVT::v2f64, Legal);
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setOperationAction(ISD::MUL , MVT::v2f64, Legal);
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setOperationAction(ISD::LOAD , MVT::v2f64, Legal);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
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setOperationAction(ISD::ADD, MVT::v2f64, Legal);
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setOperationAction(ISD::SUB, MVT::v2f64, Legal);
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setOperationAction(ISD::MUL, MVT::v2f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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}
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computeRegisterProperties();
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@ -2135,6 +2137,10 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
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Copy.getValue(1));
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}
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case ISD::SCALAR_TO_VECTOR: {
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SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
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return DAG.getNode(X86ISD::SCALAR_TO_VECTOR, Op.getValueType(), AnyExt);
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}
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}
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}
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@ -2168,6 +2174,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
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case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
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case X86ISD::Wrapper: return "X86ISD::Wrapper";
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case X86ISD::SCALAR_TO_VECTOR: return "X86ISD::SCALAR_TO_VECTOR";
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}
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}
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@ -145,6 +145,10 @@ namespace llvm {
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/// TCPWrapper - A wrapper node for TargetConstantPool,
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/// TargetExternalSymbol, and TargetGlobalAddress.
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Wrapper,
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/// SCALAR_TO_VECTOR - X86 version of SCALAR_TO_VECTOR. The destination base
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/// type does not have to match the operand type.
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SCALAR_TO_VECTOR,
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};
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// X86 specific condition code. These correspond to X86_*_COND in
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@ -24,7 +24,9 @@ def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
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// Move Instructions
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def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
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"movd {$src, $dst|$dst, $src}", []>, TB,
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"movd {$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(v2i32 (scalar_to_vector R32:$src)))]>, TB,
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Requires<[HasMMX]>;
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def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
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"movd {$src, $dst|$dst, $src}", []>, TB,
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@ -17,12 +17,14 @@
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// SSE specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
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[SDNPHasChain]>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
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[SDNPHasChain]>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86s2vec : SDNode<"X86ISD::SCALAR_TO_VECTOR",
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SDTypeProfile<1, 1, []>, []>;
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//===----------------------------------------------------------------------===//
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// SSE pattern fragments
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@ -347,12 +349,6 @@ def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
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[(set VR128:$dst, (v4f32 (undef)))]>,
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Requires<[HasSSE1]>;
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def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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// Move Instructions
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def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movaps {$src, $dst|$dst, $src}", []>;
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@ -700,7 +696,9 @@ def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
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// Move Instructions
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def MOVD128rr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
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"movd {$src, $dst|$dst, $src}", []>;
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"movd {$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v4i32 (scalar_to_vector R32:$src)))]>;
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def MOVD128rm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
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"movd {$src, $dst|$dst, $src}", []>;
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def MOVD128mr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
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@ -708,11 +706,12 @@ def MOVD128mr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
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// SSE2 instructions with XS prefix
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def MOVQ128rr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"movq {$src, $dst|$dst, $src}", []>, XS,
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"movq {$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v2i64 (scalar_to_vector VR64:$src)))]>, XS,
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Requires<[HasSSE2]>;
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def MOVQ128rm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"movq {$src, $dst|$dst, $src}", []>, XS,
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Requires<[HasSSE2]>;
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"movq {$src, $dst|$dst, $src}", []>, XS;
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def MOVQ128mr : PDI<0xD6, MRMSrcMem, (ops i64mem:$dst, VR128:$src),
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"movq {$src, $dst|$dst, $src}", []>;
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@ -731,3 +730,28 @@ def FR64ToV2F64 : PDI<0x28, MRMSrcReg, (ops VR128:$dst, FR64:$src),
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"movapd {$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v2f64 (scalar_to_vector FR64:$src)))]>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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// 128-bit vector undef's.
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def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
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// Store 128-bit integer vector values.
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def : Pat<(store (v16i8 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v8i16 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v4i32 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v2i64 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>;
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// Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
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// 16-bits matter.
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def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>,
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Requires<[HasSSE2]>;
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def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>,
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Requires<[HasSSE2]>;
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