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Fixes a bug with __builtin_vsx_lxvdw4x on Little Endian systems

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241108 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic 2015-06-30 19:45:45 +00:00
parent 60e53b2777
commit 482f87058a
2 changed files with 29 additions and 1 deletions
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5
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -9960,7 +9960,10 @@ SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
case ISD::INTRINSIC_W_CHAIN: {
MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
Chain = Intrin->getChain();
Base = Intrin->getBasePtr();
// I supppose that similarly to the store case below, this doesn't get
// us what we want. Get operand 2 instead.
//Base = Intrin->getBasePtr();
Base = Intrin->getOperand(2);
MMO = Intrin->getMemOperand();
break;
}

25
test/CodeGen/PowerPC/lxvw4x-bug.ll Normal file
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@ -0,0 +1,25 @@
; RUN: llc -O0 -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; Function Attrs: nounwind
define void @test() {
entry:
%__a.addr.i = alloca i32, align 4
%__b.addr.i = alloca <4 x i32>*, align 8
%i = alloca <4 x i32>, align 16
%j = alloca <4 x i32>, align 16
store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %i, align 16
store i32 0, i32* %__a.addr.i, align 4
store <4 x i32>* %i, <4 x i32>** %__b.addr.i, align 8
%0 = load i32, i32* %__a.addr.i, align 4
%1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8
%2 = bitcast <4 x i32>* %1 to i8*
%3 = getelementptr i8, i8* %2, i32 %0
%4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3)
; CHECK: lwa [[REG0:[0-9]+]],
; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
; CHECK: xxswapd [[REG1]], [[REG1]]
store <4 x i32> %4, <4 x i32>* %j, align 16
ret void
}
; Function Attrs: nounwind readonly
declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)