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AArch64: Pattern match integer vector abs like we do on ARM.

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This kind of pattern is emitted by the loop vectorizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221289 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2014-11-04 20:10:06 +00:00
parent c45da43b26
commit 4844826c15
2 changed files with 92 additions and 0 deletions
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22
lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -2426,6 +2426,28 @@ defm FMOV : FPMoveImmediate<"fmov">;
//===----------------------------------------------------------------------===//
defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
(v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
(ABSv8i8 V64:$src)>;
def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
(v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
(ABSv4i16 V64:$src)>;
def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
(v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
(ABSv2i32 V64:$src)>;
def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
(v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
(ABSv16i8 V128:$src)>;
def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
(v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
(ABSv8i16 V128:$src)>;
def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
(v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
(ABSv4i32 V128:$src)>;
def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
(v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
(ABSv2i64 V128:$src)>;
defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;

70
test/CodeGen/AArch64/arm64-vabs.ll
View File

@ -802,3 +802,73 @@ define <2 x i64> @sabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
%res1 = zext <2 x i32> %res to <2 x i64>
ret <2 x i64> %res1
}
define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {
; CHECK-LABEL: abspattern1:
; CHECK: abs.2s
; CHECK-NEXT: ret
%tmp1neg = sub <2 x i32> zeroinitializer, %a
%b = icmp sge <2 x i32> %a, zeroinitializer
%abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
ret <2 x i32> %abs
}
define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
; CHECK-LABEL: abspattern2:
; CHECK: abs.4h
; CHECK-NEXT: ret
%tmp1neg = sub <4 x i16> zeroinitializer, %a
%b = icmp sgt <4 x i16> %a, zeroinitializer
%abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg
ret <4 x i16> %abs
}
define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
; CHECK-LABEL: abspattern3:
; CHECK: abs.8b
; CHECK-NEXT: ret
%tmp1neg = sub <8 x i8> zeroinitializer, %a
%b = icmp slt <8 x i8> %a, zeroinitializer
%abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a
ret <8 x i8> %abs
}
define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
; CHECK-LABEL: abspattern4:
; CHECK: abs.4s
; CHECK-NEXT: ret
%tmp1neg = sub <4 x i32> zeroinitializer, %a
%b = icmp sge <4 x i32> %a, zeroinitializer
%abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
ret <4 x i32> %abs
}
define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
; CHECK-LABEL: abspattern5:
; CHECK: abs.8h
; CHECK-NEXT: ret
%tmp1neg = sub <8 x i16> zeroinitializer, %a
%b = icmp sgt <8 x i16> %a, zeroinitializer
%abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
ret <8 x i16> %abs
}
define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
; CHECK-LABEL: abspattern6:
; CHECK: abs.16b
; CHECK-NEXT: ret
%tmp1neg = sub <16 x i8> zeroinitializer, %a
%b = icmp slt <16 x i8> %a, zeroinitializer
%abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
ret <16 x i8> %abs
}
define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
; CHECK-LABEL: abspattern7:
; CHECK: abs.2d
; CHECK-NEXT: ret
%tmp1neg = sub <2 x i64> zeroinitializer, %a
%b = icmp sle <2 x i64> %a, zeroinitializer
%abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a
ret <2 x i64> %abs
}