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Add hint disassembly syntax for 16-bit Thumb hint instructions.

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Patch by Artyom Skrobov



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Barton 2013-10-18 14:09:49 +00:00
parent c439c205ba
commit 485333df71
7 changed files with 48 additions and 38 deletions
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41
lib/Target/ARM/ARMInstrThumb.td
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@ -269,30 +269,27 @@ class T1SystemEncoding<bits<8> opc>
let Inst{7-0} = opc;
}
def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
T1SystemEncoding<0x00>, // A8.6.110
Requires<[IsThumb, HasV6M]>;
def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", []>,
T1SystemEncoding<0x00>,
Requires<[IsThumb, HasV6M]> {
bits<4> imm;
let Inst{7-4} = imm;
}
def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
T1SystemEncoding<0x10>, // A8.6.410
Requires<[IsThumb, HasV6M]>;
def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
T1SystemEncoding<0x20>, // A8.6.408
Requires<[IsThumb, HasV6M]>;
def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
T1SystemEncoding<0x30>, // A8.6.409
Requires<[IsThumb, HasV6M]>;
def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
T1SystemEncoding<0x40>, // A8.6.157
Requires<[IsThumb, HasV6M]>;
def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>,
T1SystemEncoding<0x50>,
Requires<[IsThumb2, HasV8]>;
class tHintAlias<string Asm, dag Result> : tInstAlias<Asm, Result> {
let Predicates = [IsThumb, HasV6M];
}
def : tHintAlias<"hint$p $imm", (tHINT imm0_15:$imm, pred:$p)>;
def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110
def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410
def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408
def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409
def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157
def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> {
let Predicates = [IsThumb2, HasV8];
}
def : T2Pat<(int_arm_sevl), (tHINT 5)>;
// The imm operand $val can be used by a debugger to store more information
// about the breakpoint.

2
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3653,7 +3653,7 @@ def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
// A6.3.4 Branches and miscellaneous control
// Table A6-14 Change Processor State, and hint instructions
def t2HINT : T2I<(outs), (ins imm0_255:$imm), NoItinerary, "hint", "\t$imm",[]> {
def t2HINT : T2I<(outs), (ins imm0_255:$imm), NoItinerary, "hint.w", "\t$imm",[]> {
bits<3> imm;
let Inst{31-3} = 0b11110011101011111000000000000;
let Inst{2-0} = imm;

2
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -77,7 +77,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
unsigned Opcode = MI->getOpcode();
// Check for HINT instructions w/ canonical names.
if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
if (Opcode == ARM::HINT || Opcode == ARM::tHINT || Opcode == ARM::t2HINT) {
switch (MI->getOperand(0).getImm()) {
case 0: O << "\tnop"; break;
case 1: O << "\tyield"; break;

3
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -36,7 +36,8 @@ Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(ARM::tNOP);
NopInst.setOpcode(ARM::tHINT);
NopInst.addOperand(MCOperand::CreateImm(0));
NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
NopInst.addOperand(MCOperand::CreateReg(0));
}

17
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -3593,6 +3593,11 @@ _func:
wfige
yieldlt
hint.w #4
hint.w #3
hint.w #2
hint.w #1
hint.w #0
hint #4
hint #3
hint #2
hint #1
@ -3610,7 +3615,19 @@ _func:
@ CHECK: wfe.w @ encoding: [0xaf,0xf3,0x02,0x80]
@ CHECK: yield.w @ encoding: [0xaf,0xf3,0x01,0x80]
@ CHECK: nop.w @ encoding: [0xaf,0xf3,0x00,0x80]
@ CHECK: sev @ encoding: [0x40,0xbf]
@ CHECK: wfi @ encoding: [0x30,0xbf]
@ CHECK: wfe @ encoding: [0x20,0xbf]
@ CHECK: yield @ encoding: [0x10,0xbf]
@ CHECK: nop @ encoding: [0x00,0xbf]
@------------------------------------------------------------------------------
@ Unallocated wide/narrow hints
@------------------------------------------------------------------------------
hint #7
hint.w #7
@ CHECK: hint #7 @ encoding: [0x70,0xbf]
@ CHECK: hint.w #7 @ encoding: [0xaf,0xf3,0x07,0x80]
@------------------------------------------------------------------------------
@ Alternate syntax for LDR*(literal) encodings

14
test/MC/Disassembler/ARM/invalid-thumbv7.txt
View File

@ -32,15 +32,6 @@
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x6f 0xde]
#------------------------------------------------------------------------------
# Undefined encoding space for hint instructions
#------------------------------------------------------------------------------
[0x60 0xbf]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x60 0xbf]
#------------------------------------------------------------------------------
# Undefined encoding for it
#------------------------------------------------------------------------------
@ -49,10 +40,7 @@
# CHECK: potentially undefined instruction encoding
# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75]
# mask = 0
[0x50 0xbf 0x00 0x00]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x50 0xbf 0x00 0x00]
[0x50 0xbf] # hint #5; legal as the third instruction for the iteee above
# Two warnings from this block since there are two instructions in there
[0xdb 0xbf 0x42 0xbb]

7
test/MC/Disassembler/ARM/thumb2.txt
View File

@ -2707,3 +2707,10 @@
0x30 0xbf
0x10 0xbf
#------------------------------------------------------------------------------
# Unallocated hints (They execute as NOPs, but software must not use them.)
#------------------------------------------------------------------------------
[0x60 0xbf]
# CHECK: hint #6