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TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -521,7 +521,7 @@ EmitItineraries(raw_ostream &OS,
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std::vector<std::vector<InstrItinerary> >::iterator
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ProcItinListsIter = ProcItinLists.begin();
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for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
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PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
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PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
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Record *ItinsDef = PI->ItinsDef;
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if (!ItinsDefSet.insert(ItinsDef))
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@@ -532,7 +532,7 @@ EmitItineraries(raw_ostream &OS,
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// Get the itinerary list for the processor.
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assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
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std::vector<InstrItinerary> &ItinList = *ProcItinListsIter++;
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std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
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OS << "\n";
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OS << "static const llvm::InstrItinerary ";
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@@ -621,7 +621,7 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
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const std::string &Name = Processor->getValueAsString("Name");
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const std::string &ProcModelName =
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SchedModels.getProcModel(Processor).ModelName;
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SchedModels.getModelForProc(Processor).ModelName;
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// Emit as { "cpu", procinit },
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OS << " { "
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