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https://github.com/c64scene-ar/llvm-6502.git
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rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
changing the interface to allow for future changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -907,12 +907,11 @@ public:
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MVT::ValueType VT) const;
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/// isOperandValidForConstraint - Return the specified operand (possibly
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/// modified) if the specified SDOperand is valid for the specified target
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/// constraint letter, otherwise return null.
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virtual SDOperand
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isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
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SelectionDAG &DAG);
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
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std::vector<SDOperand> &Ops,
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SelectionDAG &DAG);
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//===--------------------------------------------------------------------===//
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// Scheduler hooks
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@ -3623,20 +3623,20 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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assert(!OpInfo.isIndirect &&
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"Don't know how to handle indirect other inputs yet!");
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InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
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OpInfo.ConstraintCode[0],
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DAG);
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if (!InOperandVal.Val) {
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std::vector<SDOperand> Ops;
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TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
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Ops, DAG);
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if (Ops.empty()) {
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cerr << "Invalid operand for inline asm constraint '"
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<< OpInfo.ConstraintCode << "'!\n";
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exit(1);
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}
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// Add information to the INLINEASM node to know about this input.
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unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
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unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
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AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
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TLI.getPointerTy()));
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AsmNodeOperands.push_back(InOperandVal);
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AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
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break;
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} else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
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assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
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@ -1354,12 +1354,12 @@ TargetLowering::getConstraintType(const std::string &Constraint) const {
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return C_Unknown;
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}
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/// isOperandValidForConstraint - Return the specified operand (possibly
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/// modified) if the specified SDOperand is valid for the specified target
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/// constraint letter, otherwise return null.
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SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
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char ConstraintLetter,
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SelectionDAG &DAG) {
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
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char ConstraintLetter,
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std::vector<SDOperand> &Ops,
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SelectionDAG &DAG) {
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switch (ConstraintLetter) {
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default: break;
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case 'i': // Simple Integer or Relocatable Constant
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@ -1390,19 +1390,21 @@ SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
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if (ConstraintLetter != 'n') {
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int64_t Offs = GA->getOffset();
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if (C) Offs += C->getValue();
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return DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getValueType(),
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Offs);
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Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
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Op.getValueType(), Offs));
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return;
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}
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}
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if (C) { // just C, no GV.
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// Simple constants are not allowed for 's'.
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if (ConstraintLetter != 's')
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return DAG.getTargetConstant(C->getValue(), Op.getValueType());
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if (ConstraintLetter != 's') {
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Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType()));
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return;
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}
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}
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break;
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}
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}
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return SDOperand(0,0);
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}
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std::vector<unsigned> TargetLowering::
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@ -3338,9 +3338,12 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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}
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// isOperandValidForConstraint
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SDOperand PPCTargetLowering::
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isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
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std::vector<SDOperand>&Ops,
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SelectionDAG &DAG) {
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SDOperand Result(0,0);
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switch (Letter) {
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default: break;
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case 'I':
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@ -3352,46 +3355,51 @@ isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
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case 'O':
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case 'P': {
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ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
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if (!CST) return SDOperand(0, 0); // Must be an immediate to match.
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if (!CST) return; // Must be an immediate to match.
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unsigned Value = CST->getValue();
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switch (Letter) {
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default: assert(0 && "Unknown constraint letter!");
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case 'I': // "I" is a signed 16-bit constant.
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if ((short)Value == (int)Value)
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return DAG.getTargetConstant(Value, Op.getValueType());
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Result = DAG.getTargetConstant(Value, Op.getValueType());
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break;
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case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
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case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
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if ((short)Value == 0)
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return DAG.getTargetConstant(Value, Op.getValueType());
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Result = DAG.getTargetConstant(Value, Op.getValueType());
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break;
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case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
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if ((Value >> 16) == 0)
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return DAG.getTargetConstant(Value, Op.getValueType());
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Result = DAG.getTargetConstant(Value, Op.getValueType());
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break;
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case 'M': // "M" is a constant that is greater than 31.
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if (Value > 31)
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return DAG.getTargetConstant(Value, Op.getValueType());
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Result = DAG.getTargetConstant(Value, Op.getValueType());
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break;
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case 'N': // "N" is a positive constant that is an exact power of two.
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if ((int)Value > 0 && isPowerOf2_32(Value))
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return DAG.getTargetConstant(Value, Op.getValueType());
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Result = DAG.getTargetConstant(Value, Op.getValueType());
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break;
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case 'O': // "O" is the constant zero.
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if (Value == 0)
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return DAG.getTargetConstant(Value, Op.getValueType());
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Result = DAG.getTargetConstant(Value, Op.getValueType());
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break;
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case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
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if ((short)-Value == (int)-Value)
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return DAG.getTargetConstant(Value, Op.getValueType());
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Result = DAG.getTargetConstant(Value, Op.getValueType());
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break;
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}
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break;
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}
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}
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if (Result.Val) {
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Ops.push_back(Result);
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return;
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}
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// Handle standard constraint letters.
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return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
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TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
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}
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// isLegalAddressingMode - Return true if the addressing mode represented
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@ -244,9 +244,14 @@ namespace llvm {
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
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SelectionDAG &DAG);
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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virtual void LowerAsmOperandForConstraint(SDOperand Op,
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char ConstraintLetter,
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std::vector<SDOperand> &Ops,
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SelectionDAG &DAG);
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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@ -5002,29 +5002,38 @@ X86TargetLowering::getConstraintType(const std::string &Constraint) const {
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return TargetLowering::getConstraintType(Constraint);
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}
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/// isOperandValidForConstraint - Return the specified operand (possibly
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/// modified) if the specified SDOperand is valid for the specified target
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/// constraint letter, otherwise return null.
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SDOperand X86TargetLowering::
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isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
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char Constraint,
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std::vector<SDOperand>&Ops,
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SelectionDAG &DAG) {
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SDOperand Result(0, 0);
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switch (Constraint) {
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default: break;
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case 'I':
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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if (C->getValue() <= 31)
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return DAG.getTargetConstant(C->getValue(), Op.getValueType());
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if (C->getValue() <= 31) {
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Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
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break;
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}
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}
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return SDOperand(0,0);
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return;
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case 'N':
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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if (C->getValue() <= 255)
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return DAG.getTargetConstant(C->getValue(), Op.getValueType());
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if (C->getValue() <= 255) {
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Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
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break;
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}
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}
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return SDOperand(0,0);
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return;
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case 'i': {
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// Literal immediates are always ok.
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if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op))
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return DAG.getTargetConstant(CST->getValue(), Op.getValueType());
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if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
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Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
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break;
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}
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// If we are in non-pic codegen mode, we allow the address of a global (with
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// an optional displacement) to be used with 'i'.
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@ -5054,18 +5063,24 @@ isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
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// match.
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if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
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false))
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return SDOperand(0, 0);
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return;
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Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
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Offset);
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return Op;
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Result = Op;
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break;
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}
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// Otherwise, not valid for this mode.
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return SDOperand(0, 0);
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return;
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}
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}
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return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
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if (Result.Val) {
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Ops.push_back(Result);
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return;
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}
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return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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}
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std::vector<unsigned> X86TargetLowering::
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@ -330,11 +330,13 @@ namespace llvm {
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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/// isOperandValidForConstraint - Return the specified operand (possibly
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/// modified) if the specified SDOperand is valid for the specified target
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/// constraint letter, otherwise return null.
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SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
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SelectionDAG &DAG);
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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virtual void LowerAsmOperandForConstraint(SDOperand Op,
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char ConstraintLetter,
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std::vector<SDOperand> &Ops,
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SelectionDAG &DAG);
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/// getRegForInlineAsmConstraint - Given a physical register constraint
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/// (e.g. {edx}), return the register number and the register class for the
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