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[FastISel][AArch64] Allow handling of vectors during return lowering for little endian machines.

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Allow handling of vectors during return lowering at least for little endian machines.
This was restricted in r208200 to fix it for big endian machines (according to
the comment), but it also disabled it for little endian too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217846 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
2014-09-15 23:40:10 +00:00
parent d8629f313e
commit 488f228a4f
1 changed files with 7 additions and 2 deletions
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9
lib/Target/AArch64/AArch64FastISel.cpp
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@@ -2871,11 +2871,14 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
const Value *RV = Ret->getOperand(0); const Value *RV = Ret->getOperand(0);
// Don't bother handling odd stuff for now. // Don't bother handling odd stuff for now.
if (VA.getLocInfo() != CCValAssign::Full) if ((VA.getLocInfo() != CCValAssign::Full) &&
(VA.getLocInfo() != CCValAssign::BCvt))
return false; return false;
// Only handle register returns for now. // Only handle register returns for now.
if (!VA.isRegLoc()) if (!VA.isRegLoc())
return false; return false;
unsigned Reg = getRegForValue(RV); unsigned Reg = getRegForValue(RV);
if (Reg == 0) if (Reg == 0)
return false; return false;
@@ -2891,12 +2894,14 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
return false; return false;
// Vectors (of > 1 lane) in big endian need tricky handling. // Vectors (of > 1 lane) in big endian need tricky handling.
if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1) if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 &&
!Subtarget->isLittleEndian())
return false; return false;
MVT RVVT = RVEVT.getSimpleVT(); MVT RVVT = RVEVT.getSimpleVT();
if (RVVT == MVT::f128) if (RVVT == MVT::f128)
return false; return false;
MVT DestVT = VA.getValVT(); MVT DestVT = VA.getValVT();
// Special handling for extended integers. // Special handling for extended integers.
if (RVVT != DestVT) { if (RVVT != DestVT) {