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R600/SI: Fix a crash when spilling SGPRs

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We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-06-10 21:20:38 +00:00
parent 40b0a148a2
commit 48d11b0228
2 changed files with 8 additions and 11 deletions
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18
lib/Target/R600/SIInstrInfo.cpp
View File

@ -236,17 +236,10 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
DebugLoc DL = MBB.findDebugLoc(MI); DebugLoc DL = MBB.findDebugLoc(MI);
if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) { if (RI.isSGPRClass(RC)){
SIMachineFunctionInfo::SpilledReg Spill =
MFI->SpillTracker.getSpilledReg(FrameIndex);
assert(Spill.VGPR);
BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), DestReg)
.addReg(Spill.VGPR)
.addImm(Spill.Lane);
insertNOPs(MI, 3);
} else if (RI.isSGPRClass(RC)){
unsigned Opcode; unsigned Opcode;
switch(RC->getSize() * 8) { switch(RC->getSize() * 8) {
case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break; case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break; case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break; case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
@ -260,7 +253,6 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
BuildMI(MBB, MI, DL, get(Opcode), DestReg) BuildMI(MBB, MI, DL, get(Opcode), DestReg)
.addReg(Spill.VGPR) .addReg(Spill.VGPR)
.addImm(FrameIndex); .addImm(FrameIndex);
insertNOPs(MI, 3);
} else { } else {
llvm_unreachable("VGPR spilling not supported"); llvm_unreachable("VGPR spilling not supported");
} }
@ -281,6 +273,8 @@ static unsigned getNumSubRegsForSpillOp(unsigned Op) {
case AMDGPU::SI_SPILL_S64_SAVE: case AMDGPU::SI_SPILL_S64_SAVE:
case AMDGPU::SI_SPILL_S64_RESTORE: case AMDGPU::SI_SPILL_S64_RESTORE:
return 2; return 2;
case AMDGPU::SI_SPILL_S32_RESTORE:
return 1;
default: llvm_unreachable("Invalid spill opcode"); default: llvm_unreachable("Invalid spill opcode");
} }
} }
@ -334,7 +328,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
case AMDGPU::SI_SPILL_S512_RESTORE: case AMDGPU::SI_SPILL_S512_RESTORE:
case AMDGPU::SI_SPILL_S256_RESTORE: case AMDGPU::SI_SPILL_S256_RESTORE:
case AMDGPU::SI_SPILL_S128_RESTORE: case AMDGPU::SI_SPILL_S128_RESTORE:
case AMDGPU::SI_SPILL_S64_RESTORE: { case AMDGPU::SI_SPILL_S64_RESTORE:
case AMDGPU::SI_SPILL_S32_RESTORE: {
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode()); unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) { for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
@ -348,6 +343,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
.addReg(MI->getOperand(1).getReg()) .addReg(MI->getOperand(1).getReg())
.addImm(Spill.Lane + i); .addImm(Spill.Lane + i);
} }
insertNOPs(MI, 3);
MI->eraseFromParent(); MI->eraseFromParent();
break; break;
} }

1
lib/Target/R600/SIInstructions.td
View File

@ -1538,6 +1538,7 @@ multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
} }
defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>; defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>; defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>; defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;