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R600/SI: Fix a crash when spilling SGPRs
We need to make sure only one new instruction is added when spilling otherwise the register allocator may crash. This fixes a crash in the game Antichamber. https://bugs.freedesktop.org/show_bug.cgi?id=75276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -236,17 +236,10 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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const TargetRegisterInfo *TRI) const {
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SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
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DebugLoc DL = MBB.findDebugLoc(MI);
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if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) {
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SIMachineFunctionInfo::SpilledReg Spill =
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MFI->SpillTracker.getSpilledReg(FrameIndex);
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assert(Spill.VGPR);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), DestReg)
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.addReg(Spill.VGPR)
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.addImm(Spill.Lane);
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insertNOPs(MI, 3);
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} else if (RI.isSGPRClass(RC)){
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if (RI.isSGPRClass(RC)){
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unsigned Opcode;
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switch(RC->getSize() * 8) {
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case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
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case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
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case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
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case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
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@ -260,7 +253,6 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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BuildMI(MBB, MI, DL, get(Opcode), DestReg)
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.addReg(Spill.VGPR)
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.addImm(FrameIndex);
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insertNOPs(MI, 3);
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} else {
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llvm_unreachable("VGPR spilling not supported");
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}
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@ -281,6 +273,8 @@ static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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return 2;
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case AMDGPU::SI_SPILL_S32_RESTORE:
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return 1;
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default: llvm_unreachable("Invalid spill opcode");
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}
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}
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@ -334,7 +328,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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case AMDGPU::SI_SPILL_S64_RESTORE: {
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case AMDGPU::SI_SPILL_S64_RESTORE:
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case AMDGPU::SI_SPILL_S32_RESTORE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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@ -348,6 +343,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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.addReg(MI->getOperand(1).getReg())
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.addImm(Spill.Lane + i);
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}
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insertNOPs(MI, 3);
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MI->eraseFromParent();
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break;
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}
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@ -1538,6 +1538,7 @@ multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
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}
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defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
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defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
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defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
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defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
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