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Thumb assembly parsing and encoding for LDRB.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-19 18:49:59 +00:00
parent 09f6e0dfda
commit 48ff5ffe9e
3 changed files with 38 additions and 0 deletions
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2
lib/Target/ARM/ARMInstrThumb.td
View File

@ -179,11 +179,13 @@ def t_addrmode_is2 : Operand<i32>,
// t_addrmode_is1 := reg + imm5 // t_addrmode_is1 := reg + imm5
// //
def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
def t_addrmode_is1 : Operand<i32>, def t_addrmode_is1 : Operand<i32>,
ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
let EncoderMethod = "getAddrModeISOpValue"; let EncoderMethod = "getAddrModeISOpValue";
let DecoderMethod = "DecodeThumbAddrModeIS"; let DecoderMethod = "DecodeThumbAddrModeIS";
let PrintMethod = "printThumbAddrModeImm5S1Operand"; let PrintMethod = "printThumbAddrModeImm5S1Operand";
let ParserMatchClass = t_addrmode_is1_asm_operand;
let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
} }

16
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -628,6 +628,15 @@ public:
int64_t Val = Mem.OffsetImm->getValue(); int64_t Val = Mem.OffsetImm->getValue();
return Val >= 0 && Val <= 124 && (Val % 4) == 0; return Val >= 0 && Val <= 124 && (Val % 4) == 0;
} }
bool isMemThumbRIs1() const {
if (Kind != Memory || Mem.OffsetRegNum != 0 ||
!isARMLowRegister(Mem.BaseRegNum))
return false;
// Immediate offset in range [0, 31].
if (!Mem.OffsetImm) return true;
int64_t Val = Mem.OffsetImm->getValue();
return Val >= 0 && Val <= 31;
}
bool isMemThumbSPI() const { bool isMemThumbSPI() const {
if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP) if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
return false; return false;
@ -1000,6 +1009,13 @@ public:
Inst.addOperand(MCOperand::CreateImm(Val)); Inst.addOperand(MCOperand::CreateImm(Val));
} }
void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
Inst.addOperand(MCOperand::CreateImm(Val));
}
void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!"); assert(N == 2 && "Invalid number of operands!");
int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0; int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;

20
test/MC/ARM/basic-thumb-instructions.s
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@ -210,3 +210,23 @@ _func:
ldr r1, [r2, r3] ldr r1, [r2, r3]
@ CHECK: ldr r1, [r2, r3] @ encoding: [0xd1,0x58] @ CHECK: ldr r1, [r2, r3] @ encoding: [0xd1,0x58]
@------------------------------------------------------------------------------
@ LDRB (immediate)
@------------------------------------------------------------------------------
ldrb r4, [r3]
ldrb r5, [r6, #0]
ldrb r6, [r7, #31]
@ CHECK: ldrb r4, [r3] @ encoding: [0x1c,0x78]
@ CHECK: ldrb r5, [r6] @ encoding: [0x35,0x78]
@ CHECK: ldrb r6, [r7, #31] @ encoding: [0xfe,0x7f]
@------------------------------------------------------------------------------
@ LDRB (register)
@------------------------------------------------------------------------------
ldrb r6, [r4, r5]
@ CHECK: ldrb r6, [r4, r5] @ encoding: [0x66,0x5d]