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ret 0; works, not much else

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still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23832 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
2005-10-20 00:28:31 +00:00
parent 9811ea4567
commit 4907d22a90
7 changed files with 225 additions and 138 deletions
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8
lib/Target/Alpha/AlphaTargetMachine.cpp
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@ -32,6 +32,9 @@ namespace llvm {
cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
cl::desc("Enable LSR for Alpha (beta option!)"),
cl::Hidden);
cl::opt<bool> EnableAlphaDAG("enable-dag-isel-for-alpha",
cl::desc("Enable DAG ISEL for Alpha (beta option!)"),
cl::Hidden);
}
unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
@ -94,7 +97,10 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM,
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
PM.add(createAlphaPatternInstructionSelector(*this));
if (EnableAlphaDAG)
PM.add(createAlphaISelDag(*this));
else
PM.add(createAlphaPatternInstructionSelector(*this));
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));