From 490c7d97737ea7719efcea7321d3cfa3984b0027 Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Wed, 16 Jan 2013 00:07:45 +0000 Subject: [PATCH] Akira, Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 5 ++++- .../Mips/Disassembler/MipsDisassembler.cpp | 16 ++++++++++++++++ lib/Target/Mips/MipsRegisterInfo.td | 2 +- test/MC/Disassembler/Mips/mips32.txt | 6 ++++++ test/MC/Disassembler/Mips/mips32_le.txt | 6 ++++++ test/MC/Mips/mips-alu-instructions.s | 5 +++++ test/MC/Mips/mips64-alu-instructions.s | 6 ++++++ 7 files changed, 44 insertions(+), 2 deletions(-) diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 57338df53cb..482210673a5 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1071,6 +1071,9 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl &Operands) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseHW64Regs(SmallVectorImpl &Operands) { + + if (!isMips64()) + return MatchOperand_NoMatch; //if the first token is not '$' we have error if (Parser.getTok().isNot(AsmToken::Dollar)) return MatchOperand_NoMatch; @@ -1088,7 +1091,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl &Operands) { MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S, Parser.getTok().getLoc()); - op->setRegKind(MipsOperand::Kind_HWRegs); + op->setRegKind(MipsOperand::Kind_HW64Regs); Operands.push_back(op); Parser.Lex(); // Eat reg number diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 1efeffd3281..9560f3fc524 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -128,6 +128,11 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -454,6 +459,17 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + //Currently only hardware register 29 is supported + if (RegNo != 29) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index c6eb0e1e87a..f93dd86c176 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand { let ParserMatchClass = HWRegsAsmOperand; } -def HW64RegsOpnd : RegisterOperand { +def HW64RegsOpnd : RegisterOperand { let ParserMatchClass = HW64RegsAsmOperand; } diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index a1933190b14..70224860bc7 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x7c 0x05 0xe8 0x3b diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 08b36726baf..48fa8e2c7fa 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x3b 0xe8 0x05 0x7c diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index ee2a9a0db45..52fd900091d 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -81,6 +81,10 @@ # CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00] # CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00] # CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] add $9,$6,$7 add $9,$6,17767 addu $9,$6,-15001 @@ -98,3 +102,4 @@ neg $6,$7 negu $6,$7 move $7,$8 + rdhwr $5, $29 diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index a77ed43ff10..d30ddeee717 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -78,6 +78,11 @@ # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] # CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] # CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] + dadd $9,$6,$7 dadd $9,$6,17767 daddu $9,$6,-15001 @@ -92,3 +97,4 @@ multu $3,$5 dsubu $4,$3,$5 move $7,$8 + rdhwr $5, $29