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[FastISel][AArch64] Use a new helper function to determine if a value type is supported. NFCI.

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FastISel for AArch64 supports more value types than are actually legal. Use a
dedicated helper function to reflect this.

It is very similar to the isLoadStoreTypeLegal function, with the exception
that vector types are not supported yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-09-02 22:33:53 +00:00
parent 73d86aa56a
commit 4919b697c2
1 changed files with 25 additions and 6 deletions
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31
lib/Target/AArch64/AArch64FastISel.cpp
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@ -134,6 +134,7 @@ private:
// Utility helper routines.
bool isTypeLegal(Type *Ty, MVT &VT);
bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
bool isTypeSupported(Type *Ty, MVT &VT);
bool isValueAvailable(const Value *V) const;
bool ComputeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
bool ComputeCallAddress(const Value *V, Address &Addr);
@ -680,6 +681,26 @@ bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
return false;
}
/// \brief Determine if the value type is supported by FastISel.
///
/// FastISel for AArch64 can handle more value types than are legal. This adds
/// simple value type such as i1, i8, and i16.
/// Vectors on the other side are not supported yet.
bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT) {
if (Ty->isVectorTy())
return false;
if (isTypeLegal(Ty, VT))
return true;
// If this is a type than can be sign or zero-extended to a basic operation
// go ahead and accept it now.
if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
return true;
return false;
}
bool AArch64FastISel::isValueAvailable(const Value *V) const {
if (!isa<Instruction>(V))
return true;
@ -1571,7 +1592,7 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
} else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
MVT SrcVT;
if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
(isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
(isTypeSupported(TI->getOperand(0)->getType(), SrcVT))) {
unsigned CondReg = getRegForValue(TI->getOperand(0));
if (!CondReg)
return false;
@ -3295,7 +3316,7 @@ bool AArch64FastISel::SelectMul(const Instruction *I) {
bool AArch64FastISel::SelectShift(const Instruction *I) {
MVT RetVT;
if (!isLoadStoreTypeLegal(I->getType(), RetVT))
if (!isTypeSupported(I->getType(), RetVT))
return false;
if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
@ -3306,16 +3327,14 @@ bool AArch64FastISel::SelectShift(const Instruction *I) {
const Value *Op0 = I->getOperand(0);
if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
MVT TmpVT;
if (isValueAvailable(ZExt) &&
isLoadStoreTypeLegal(ZExt->getSrcTy(), TmpVT)) {
if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), TmpVT)) {
SrcVT = TmpVT;
IsZExt = true;
Op0 = ZExt->getOperand(0);
}
} else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
MVT TmpVT;
if (isValueAvailable(SExt) &&
isLoadStoreTypeLegal(SExt->getSrcTy(), TmpVT)) {
if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), TmpVT)) {
SrcVT = TmpVT;
IsZExt = false;
Op0 = SExt->getOperand(0);